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2021-02-09soc/amd/picasso/cpu: move get_cpu_count to common codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0690787f492d764a20a4219822eb10fb5cd86de0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-08soc/amd/common/memmap: add comment about types in memmap_early_dramFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reported-by: Angel Pons <th3fanbus@gmail.com> Change-Id: I295bfcb05571492adbe81ffc579a835be4abffe1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-07soc/amd/picasso: Move memmap_early_dram to common blocksRaul E Rangel
We need the same functionality for cezanne. TEST=Boot ezknil Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0800c662bb473eb571c74e76a8247298f534b53f Reviewed-on: https://review.coreboot.org/c/coreboot/+/50337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01soc/amd/common: Use only byte access for old GPIOKyösti Mälkki
Change-Id: I06ec29845d051d9b90ab6f3cfb269ad5e6b75ea8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-01soc/amd/common: Drop ACPIMMIO GPIO bank separationKyösti Mälkki
It's assumed in ASL already that the banks appear one after other in ACPIMMIO space. There is no need for the separation of accessor functions by name. Change-Id: I4c8c3f2028ca89dca5c7f0548fcd18e1045999d6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-31soc/amd/*/psp: move MSR_CU_CBBCFG to common and rename to MSR_PSP_ADDRFelix Held
TEST=Checked that the MSR is the same for Stoneyridge, Picasso and Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id15715ed1c17f4fc475985dcb1c31a83713ee65c Reviewed-on: https://review.coreboot.org/c/coreboot/+/50149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-25soc/amd: Refactor ACPI power state and ELOGKyösti Mälkki
Change-Id: Ib7423c8d80355871393c377ebaffdfe2846d8852 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-19soc/amd/picasso,stoneyridge: Unify set_nvs_sws()Kyösti Mälkki
Change-Id: I673f038b4ce3c4141db128a65be71e7a242dfd28 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-14soc/amd/piasso/uart: move get_uart_base prototype to common code headerFelix Held
This will result in less code duplication when the common AMD SoC UART support gets used for more AMD SoCs. Change-Id: Id1786f32324de3e3947d792c599e2019705c5a85 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49373 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-13soc/amd: Rename to pm_fill_gnvs()Kyösti Mälkki
Change-Id: I80f92bed737904e6ffc858b45459405fe76f1d04 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-11soc/amd/picasso: Separate GPIO define into gpio_defs.hEric Lai
Separate GPIO define into gpio_defs.h, then we can use it in asl include. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If2a779eae228f621e77610889205853de2fb179a Reviewed-on: https://review.coreboot.org/c/coreboot/+/49216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-16soc/amd/common: Use only byte access for IOMUXKyösti Mälkki
Change-Id: Ia3c4fb41b5851b1c0ffc6bbec7d1c051e232fc94 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42978 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-15soc/amd/common: Redo ACPIMMIO_BASE and _BANKKyösti Mälkki
Change-Id: I31f2d04d9fc8bdd9e270fb3cb48d71f215999a50 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42894 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-15soc/amd/common: Refactor SMBus base argumentsKyösti Mälkki
Replace SMBus base addresses with proper symbols. Change-Id: I5e0ebd7609c5c83d0e443ffba74dae68017d3ebc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42074 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-12soc/amd/common: Remove SMBus host word accessorsKyösti Mälkki
SMBus controller has byte-wide registers. Remove the word accessors. Change-Id: If396108308bc8303d84458039b9529ecd83276c9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-12soc/amd/common: Refactor ACPIMMIO posted writesKyösti Mälkki
Change-Id: Ic1a5c17c789dd79fea8f348d1a9d32d4301ced88 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42825 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11soc/amd/picasso: factor out write_resume_eip to common codeFelix Held
Change-Id: I24454aa9e2ccc98b2aceb6b189e072e6e50b8b30 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09soc/amd: factor out functionality to print last reset sourceFelix Held
Change-Id: I5cec38dac7ea27aa316f5dd4f91ed84627a0f937 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09soc/amd: factor out legacy I/O and cf9 decode enable functionsFelix Held
Replace sb prefix with fch prefix, since those are all FCHs and no south bridges any more. Verstage on PSP uses the I/O access mechanism instead of the MMIO one, so keep a separate function for that, but also move it to the common mmio_util file to have them all in one place. Change-Id: I47dac9ee3d9e27f7b7a5fddab17cf4fc10de6c3e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48435 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09soc/amd/common/block/smbus: refactor fch_smbus_initFelix Held
Move the setup of the base address to a separate function and explicitly set the SMBUS and ASF I/O port decode even though it is expected to already be set after reset. Change-Id: I8072ab78985021d19b6528100c674ecdd777e62e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09soc/amd: factor out PM_DECODE_EN register definitionsFelix Held
Change-Id: I005709a8780725339e7c08fbfff94e89c8ef26da Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09soc/amd: remove unused PM_ISA_CONTROL definitionsFelix Held
ACPIMMIO_DECODE_REGISTER_04 is the definition in the common ACPIMMIO code block that actually gets used. Also fix the indentation of the ACPIMMIO register decode defines in the common code. Change-Id: Ib2c460541be768fe05d8cc3d19a14dbd9c114a45 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-02soc/amd: factor out common SMI/SCI enums and function prototypesFelix Held
At least a part or the remaining definitions in the soc-specific smi.h files are also common, but those have to be verified more closely. Change-Id: I5a3858e793331a8d2ec262371fa22abac044fd4a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-02soc/amd/common/smbus: remove misleading definitionFelix Held
SMBHST_STAT_NOERROR was a redefinition of SMBHST_STAT_INTERRUPT that was used in smbus_wait_until_done. Remove the misleading bit definition that also didn't correspond with the register definitions and replace it with the definition of the actual bit that gets checked. Also add a comment that the code actually checks the IRQ status flag to see if the last command is already completed. Change-Id: I1a58fe0d58d3887dd2e83320e977a57e271685b3 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-02soc/amd: factor out fch_smbus_initFelix Held
Change-Id: I6df9323dc4e7ca99fd5368f0262e850c0aca5c54 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-02soc/amd: factor out SMBUS controller registers into common headerFelix Held
The patch also rewrites the bit definition using shifts to make them easier to read. The older non-SoC chips can probably also use the new header file, but for this patch the scope is limited to soc/amd, since the older non-SoC chips don't use the SMBUS controller code in soc/amd/common. TEST=Timeless build for amd/mandolin and amd/gardenia doesn't change. Change-Id: Ifd5e7e64a41f1cb20cdc4d6ad1e675d7f2de352b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-02soc/amd: factor out common AOAC device enable and status query functionsFelix Held
The code on Stoneyridge didn't set the FCH_AOAC_TARGET_DEVICE_STATE bits to FCH_AOAC_D0_INITIALIZED like the code for Picasso does, but that is the default value after reset for those bits on both platforms. Change-Id: I7cae23257ae54da73b713fe88aca5edfa4656754 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-02soc/amd: factor out common AOAC definitionsFelix Held
The register locations and bit definitions are the same for Stoneyridge and Picasso. Since not all devices are present on all SoCs, keep those numbers in the SoC-specific code. Change-Id: Ib882927e399031c376738e5a35793b3d7654b9cf Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-16soc/amd/common/block: drop double underscores from include guardsFelix Held
Since coreboot is written in C and not C++, having the double underscores as a prefix is not an issue, but it also doesn't add much information, so drop them and the trailing ones as well. Change-Id: I1028fb9097efab8ffae5ffa9fe85a97feebc78a9 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47583 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-15soc/amd/common: factor out SMU code from PicassoFelix Held
The SMU mailbox access code from Picasso can be reused in the next generation, so factor out the code to soc/amd/common/block/smu. Since the mailbox register offsets in the indirect address space, the number of arguments and the message IDs don't always match between different devices, keep those in the soc-specific directories. Change-Id: Ibaf5b91ab35428e4c771e7163c6e0c4fc50371e7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-13soc/amd: factor out _SOC_DEV macro into common blockFelix Held
TEST=Timeless build doesn't change for Mandolin and Gardenia. Change-Id: I1aef68459569536207697bfca407145a7b5334f4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-13soc/amd/common/block/include: make include guards more uniformFelix Held
TEST=Timeless build doesn't change for Mandolin and Gardenia. Change-Id: I5d3ae1459c333658f4c86388f1822d92ca13c658 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-09-21soc/amd: Drop unneeded empty linesElyes HAOUAS
Change-Id: Ib262955a1d26681c796c4b10d2b336f2715824d0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-08-19soc/amd/common: add gpio subsystem event reportingAaron Durbin
In order to log gpio events for wake purposes the state of the gpio subsystem should be snapshotted. Add the ability to capture state of gpio subystem as well as saving up to 16 gpios that indicate their wake status. Likewise, provide the eventlog additions based on state. BUG=b:159947207 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I49fca56c87543aa8aad0eb7da5c5cb570c4349d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44534 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17soc/amd/common: removed unused functionsAaron Durbin
Now that all users of the functions manipulating global state and using soc-specific objects are removed remove those functions. BUG=b:159947207 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I18c4c8b0c7852dde8cf0b6b3f11e43e15c3ce155 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-17soc/amd/common: add acpi_fill_gnvs()Aaron Durbin
In order to reduce code duplication provide an acpi_fill_gnvs() helper function. Intent is to move stoneyridge and picasso over to using this common implementation instead of duplicating it. BUG=b:159947207 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I21c6e2c24eaf42f31ae57c05df7f633d7dc266d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-17soc/amd/common: add single function ACPI PM1 GPE helpersAaron Durbin
The existing code in common/block/acpi is mixing multiple operations: saving things to cbmem in common code but then soc code uses that information, reliant upon soc-specific struct soc_power_reg object, and only saving/snapshotting ACPI registers very deep in ramstage. To unwind the above provide some functions that are more targeted: - Add struct acpi_pm_gpe_state object - Add acpi_fill_pm_gpe_state() - Add acpi_pm_gpe_add_events_print_events() - Add acpi_clear_pm_gpe_status() BUG=b:159947207 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ia7afed2861343802b3c78728784f7cfaf6f53f62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-28src/soc/amd: Add include <types.h>Elyes HAOUAS
BIT(x) needs <types.h>. Change-Id: Icaeda969cae52d9c62d976db4ead0e734efa838c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-27soc/amd/common: Move spi access functions into their own fileMartin Roth
Because there was a lot of discussion about the size increase, I also looked at the impact of calling the get_spi_bar() function vs reading spi_base directly and just not worring about whether or not spi_base was already set. Using the spi_base variable directly is 77 bytes bytes for all 6 functions. it's roughly double the size to call the function at 153 bytes. This was almost entirely due to setting up a call stack. If we add an assert into each function to make sure that the spi_base variable is set, it doubles from the size of the function call to 333 bytes. For my money, the function call is the best bet, because it not only protects us from using spi_base before it's set, it also gets the value for us (at least on x86, on the PSP, it still just dies.) BUG=b:161366241 TEST: Build Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I0b0d005426ef90f09bf090789acb9d6383f17bd2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-07-26soc/amd/common: Refactor and consolidate code for spi baseMartin Roth
Previously, the spi base address code was using a number of different functions in a way that didn't work for use on the PSP. This patch consolidates all of that to a single saved value that gets the LPC SPI base address by default on X86, and allows the PSP to set it to a different value. BUG=b:159811539 TEST=Build with following patch to set the SPI speed in psp_verstage. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I50d9de269bcb88fbf510056a6216e22a050cae6b Reviewed-on: https://review.coreboot.org/c/coreboot/+/43307 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23soc/amd/common/gpio: Fix definition of GPIO_INT_ENABLE_STATUS_DELIVERYFurquan Shaikh
This change fixes the definition of `GPIO_INT_ENABLE_STATUS_DELIVERY` to use `GPIO_INT_ENABLE_DELIVERY` instead of `GPIO_INT_ENABLE_STATUS_DELIVERY`. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I64d912200779875cf121cec4476fd39de74c0223 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-17soc/amd/common/gpio: Add macro for PAD_NCFurquan Shaikh
This change adds a macro `PAD_NC` for configuring no-connect pads. This configures the pad as input with pull-down. Change-Id: I47c41c88ccfebe2c5dd9a24f85a120af9c8f56b5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-14soc/amd/common/block/include/amdblocks/acpi.h: Add missing <types.h>Elyes HAOUAS
BIT(x) needs <types.h> Change-Id: I5dc0d45567ae9879a7e12f2ccc48929d2abc9456 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-14src: Remove unused 'include <stdint.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <stdint.h>' -- src/) <(git grep -l 'int8_t\|int16_t\|int32_t\|int64_t\|intptr_t\|intmax_t\|s8\|u8\|s16\|u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|INT16_MIN\|INT16_MAX\|INT32_MIN\|INT32_MAX\|INT64_MIN\|INT64_MAX\|INTMAX_MIN\|INTMAX_MAX' -- src/) |grep -v vendorcode |grep '<' Change-Id: I5e14bf4887c7d2644a64f4d58c6d8763eb74d2ed Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41827 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-11arch/x86: Drop CBMEM_TOP_BACKUPKyösti Mälkki
Code has evolved such that there seems to be little use for global definition of cbmem_top_chipset(). Even for AMD we had three different implementations. Change-Id: I44805aa49eab526b940e57bd51cd1d9ae0377b4b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43326 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03soc/amd/common: fix eSPI virtual wire polarity encodingAaron Durbin
eSPI interrupts are active level high. The eSPI polarity register in the chipset inverts incoming signals if the corresonding bit is 0 in the register. Therefore, all active high (edge or level) virtual wire interrupts need to ensure they are not inverted. And really the sender of the interrupts should be conforming to the the eSPI spec. As such inverting any signals should not be necessary, but this register in the chipset allows for fixing up those misbehaviors. BUG=b:157984427 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I7346bb0484506d96d7ab2e6d046ffa0571683a48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-30soc/amd/common/gpio: Add new helper macro PAD_CFG_STRUCT_FLAGSFurquan Shaikh
`flags` field of soc_amd_gpio structure is set only for SCI and SMI configurations. This change adds a new helper macro PAD_CFG_STRUCT_FLAGS that allows setting of all soc_amd_gpio members including `flags` field. This can be used directly by PAD_SCI and PAD_SMI. For all other pad configurations, PAD_CFG_STRUCT macro uses PAD_CFG_STRUCT_FLAGS with flags set to 0. This allows dropping of redundant parameter 0 for flags for all other pad configurations. BUG=b:159944426 Change-Id: I835b62f5502375ffc4215548b51338a67546d699 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42876 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30soc/amd/gpio, mb/{amd,google}: Configure pads using a single entry in GPIO ↵Furquan Shaikh
configuration table Currently, for Stoneyridge and Picasso mainboards, pads that are configured for SCI/SMI/WAKE need to have multiple entries in the configuration table - one for PAD_GPI and other for the special configuration that is required. This requires a very specific ordering of pads within the table and is prone to errors because of conflicting params provided to the different entries for the same pad. This also does not work very well with the concept of override GPIOs where the entry in base table is overridden with the first matched entry from the override table. This change updates the way GPIO configuration is handled for special routing like SCI/SMI/WAKE/DEBOUNCE by setting the control field of soc_amd_gpio structure in the macros performing these configurations. Also, program_gpios() is updated to perform a write to GPIO control register instead of read-modify-write. This is because mainboard is expected to provide only a single configuration entry for each pad within a given table. Thus, there is no need to preserve earlier configuration. Mainboards that were providing multiple entries for a single pad are updated accordingly. BUG=b:159944426 Change-Id: I3364dc2982d66c4e33c2b4e6b0b97641ebea27f0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42875 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30soc/amd/common/gpio: Use gpio_setbits32()Furquan Shaikh
Some codepaths want to set selected bits of a hardware register to match those of a given variable in memory. Provide a helper function for this purpose and use it in gpio_set(), gpio_input_pulldown() and gpio_input_pullup(). This change also adds GPIO_PULL_MASK and updates GPIO_OUTPUT_MASK to include all bits dealing with pull and output respectively. Change-Id: I4413d113dff550900348a44f71b949b7547a9cfc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-30soc/amd/common/gpio: Add macros for setting fields of soc_amd_gpioFurquan Shaikh
This change adds helper macro PAD_CFG_STRUCT for setting the fields of `soc_amd_gpio`. Additionally, macros are added for different operations i.e. pull, output, trigger, int_enable, event_trigger, wake_enable, debounce, etc. All GPIO configuration macros are updated to use PAD_CFG_STRUCT instead of setting the fields directly. BUG=b:159944426 Change-Id: I03535d2da0c05f72c4163fa30d72f9c6df44908b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42872 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-12 18:35:23 +0000