summaryrefslogtreecommitdiff
path: root/src/soc/amd/common/block/lpc
AgeCommit message (Collapse)Author
2020-05-07soc/amd/common/block/lpc: Use standard pci_dev_ops_pciFurquan Shaikh
AMD common block LPC driver does not really need a custom ops_pci structure. This change drops the lops_pci and instead set .ops_pci to the default pci_dev_ops_pci. BUG=b:154445472 Change-Id: Ia06eed04097739c3e21dc13e056a2120ff5eb382 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-05soc/amd/common/block/lpc: Add lpc_disable_spi_rom_sharingRaul E Rangel
If a Picasso platform wants to use GPIO 67 it must disable ROM sharing. Otherwise ROM access is incredibly slow. BUG=b:153502861 TEST=Build trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia9ab3803a2f56f68c1164bd241fc3917a3ffcf2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/40951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-28amd/family17h: Add PCI device IDs for all controllers in AMD Family17hFurquan Shaikh
This change adds all the missing PCI device IDs for AMD Family 17h. IDs that were already present are updated to include _FAM17H_ in the name instead of _PCO_ and _DALI_. This ensures that the PCI IDs match the family and models as per the PPR. In cases where the controller is present only on certain models, _MODEL##H_ is also included in the name. BUG=b:153858769 BRANCH=None TEST=Verified that trembyle and dalboz still build. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ia767d32ec22f5e58827e7531c0d3d3bac90d3425 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-24soc/amd/picasso/i2c: don't initialize I2C4 as master and refactor codeMartin Roth
I2C0&1 are either not available or not functional. Add place holders instead, so that the array index matches the I2C controller number. I2C4 is slave device only, so do not initialize it as I2C host controller. Also do some slight refactoring. BUG=b:153152871 BUG=b:153675916 Change-Id: I397b074ef9c14bf6a4f6680696582f5173a5d0d3 Signed-off-by: Martin Roth <martinroth@chromium.org> Signed-off-by: Paul Ma <magf@bitland.corp-partner.google.com> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1897071 Reviewed-on: https://chromium-review.googlesource.com/2057468 Reviewed-on: https://chromium-review.googlesource.com/2094855 Reviewed-on: https://chromium-review.googlesource.com/2149870 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40247 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-05soc/amd: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I22fffa0eab006be2bad4d3dd776b22ad9830faef Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-02Trim `.acpi_fill_ssdt_generator` and `.acpi_inject_dsdt_generator`Nico Huber
These two identifiers were always very confusing. We're not filling and injecting generators. We are filling SSDTs and injecting into the DSDT. So drop the `_generator` suffix. Hopefully, this also makes ACPI look a little less scary. Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: David Guckian Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-18soc: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-10-20soc/amd/common/lpc: Add SuperIO decode functionMarshall Dawson
The LPC-ISA bridge supports two ranges for SuperIO control registers. Add a generic function to allow a mainboard to enable the appropriate range. Provide #define values that are more descriptive than the register's field names. Change-Id: Ic5445cfc137604cb1bb3ee3ea4c3a4ebdb9a9cab Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35271 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-08device: Use scan_static_bus() over scan_lpc_bus()Nico Huber
Devices behind LPC can expose more buses (e.g. I2C on a super-i/o). So we should scan buses on LPC devices, too. Change-Id: I0eb005e41b9168fffc344ee8e666d43b605a30ba Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29474 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-09soc/amd/common/lpc: Add decode disable functionMarshall Dawson
It is already trivial to set D14F3x44 to 0, but add a function to wipe both that and the settings in D14F3x48, along with x48's associated addresses. Change-Id: Ibec25562b2a1568681aea7caf86f00094c436a50 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-07-03soc/amd/common/lpc: Add Picasso IDMarshall Dawson
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I02e6fdcd6685e0dd3fa7872b054ebe508157a0ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/33758 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Move LPC support to commonMarshall Dawson
AMD devices traditionally have the LPC-ISA bus at 14.3 and the definition has been very consistent. Relocate the feature from stoneyridge into common/block. BUG=b:131682806 Change-Id: I8d7175b8642bb17533bb2287b3e3ee3d52e85a75 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32653 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 04:33:09 +0000