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2019-04-23src: Add missing include 'console.h'Elyes HAOUAS
Change-Id: Ie21c390ab04adb5b05d5f9760d227d2a175ccb56 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-04-06src: Use include <delay.h> when appropriateElyes HAOUAS
Change-Id: I23bc0191ca8fcd88364e5c08be7c90195019e399 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian
2019-03-25Fix up remaining boolean uses of CONFIG_XXX to CONFIG(XXX)Julius Werner
This patch cleans up remaining uses of raw boolean Kconfig values I could find by wrapping them with CONFIG(). The remaining naked config value warnings in the code should all be false positives now (although the process was semi-manual and involved some eyeballing so I may have missed a few). Change-Id: Ifa0573a535addc3354a74e944c0920befb0666be Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-20src: Use 'include <string.h>' when appropriateElyes HAOUAS
Drop 'include <string.h>' when it is not used and add it when it is missing. Also extra lines removed, or added just before local includes. Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-06src: Drop unused include <arch/acpi.h>Elyes HAOUAS
Change-Id: I1f44ffeb54955ed660162a791c6281f292b1116a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-02-25soc/amd/common: Fix AmdLateRunApTask()Kyösti Mälkki
Third parameter ConfigPtr of the callout is of type AP_EXE_PARAMS and needs to be passed back to AGESA with AmdLateRunApTask() call. Change-Id: I1dad64b955b53bd19363737665235f95aa3d451e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/27277 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-15soc/amd/common: Move PI refcode loaderKyösti Mälkki
The moved functions are only about locating and loading the refcode blobs. Separate them from the actual calls into the blob. Eventually previous binaryPI blobs should be unified to share same loader code. Change-Id: I68885e7f855b195c178e746c8f3f0f49166d0def Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-02-12soc/amd/common: Don't use CAR_GLOBALArthur Heymans
All platforms using this code have NO_CAR_GLOBAL_MIGRATION. Change-Id: I422d5637caa1b55fa6bad30d25f5e34cbba40851 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-02-12soc/amd/common: Remove redundant ACPI S3 testKyösti Mälkki
Possible allowance to do wakeup is already evaluated early in romstage, so these tests are redundant. Change-Id: I7c7a9ecbfcb82790e477d906a00f9749103b4045 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/27276 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-16buildsystem: Promote rules.h to default includeKyösti Mälkki
Does not fix 3rdparty/, *.S or *.ld or yet. Change-Id: I66b48013dd89540b35ab219d2b64bc13f5f19cda Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/17656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-06device: Use pcidev_path_on_root()Kyösti Mälkki
Change-Id: I2e28b9f4ecaf258bff8a062b5a54cb3d8e2bb9b0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-05src/(device/lib/soc): Remove unused variablesRichard Spiegel
When building grunt with flags set to detect variables that get a value but then are unused, there are 5 instances that causes error (unused variable). In most cases it's enough to simply remove the variable. Other instances, is better to simply use the variables (one instance it's a return value, on the other instance using the variables makes code more readable). BUG=b:120260448 TEST=Build and boot grunt. Change-Id: I0d00fb6a42db20afb34c76b9445a741a57096ead Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/29985 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16soc/amd: Convert from AMD units to coreboot unitsRichard Spiegel
There are several files under soc/amd that use units defined by file porting.h. These units use upper case, and are not recognized by checkpatch, thus causing problems when defining a pointer (request to use space before and after the star symbol). These are the definitions from porting.h showing the units that this patch will change and their coreboot definitions (not all are actually used): typedef uintptr_t UINTN; typedef int64_t INT64; typedef uint64_t UINT64; typedef int32_t INT32; typedef uint32_t UINT32; typedef int16_t INT16; typedef uint16_t UINT16; typedef int8_t INT8; typedef uint8_t UINT8; typedef char CHAR8; typedef unsigned short CHAR16; typedef unsigned char BOOLEAN; typedef void VOID; BUG=b:118775313 TEST=Build and boot grunt. Change-Id: Ic1bd64d6224a030a65d23decabf0e602cee02871 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-06soc/amd/common: Fix function formatingRichard Spiegel
There are functions within heapmanager.c that have a space between the function name and open parenthesis. Remove these spaces. BUG=b:117950051 TEST=build grunt. Change-Id: I2120d9d5f663453b6201d1872f29c6dc4abd6191 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29230 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-30soc/amd/stoneyridge: Set IOMMU support to follow device settingMartin Roth
Instead of forcing the IOMMU to be enabled, change it to only be enabled if the device is enabled in devicetree. BUG=b:118612241 TEST=Verify that IOMMU is disabled. Change-Id: I6cfd6c81f47de23c54a49ec7cf87b219215ced5e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/29343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2018-10-25soc/amd/common/def_callouts.c: Prefer using '"%s...", __func__'Richard Spiegel
In function agesa_GfxGetVbiosImage(), the function name is used in a print string. Use __func__ instead. BUG=b:117642170 TEST=Build grunt. Change-Id: I95a042bd95cc729305a8a008e3bb464f60c2668d Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-10-25soc/amd/common/pi: Correct top of DRAM reporting by AGESAMarshall Dawson
Accurately reflect the intention of the syslimit value returned from AmdInitPost(). Assume FFs for the non-present bits. BUG=b:118178425 TEST=Boot Grunt and verify reported value = TOM2-1. Change-Id: Ie8ea4fcbfd52c46ad441890f0decaf0f55816cfd Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-22soc/amd: Implement common reset APINico Huber
Add an `amdblocks` internal API and rename soft_reset() => warm_reset() hard_reset() => cold_reset() as these terms are commonly used in the surrounding code. On Stoney Ridge, make board_reset() call cold_reset() to keep current behaviour of common code calling hard_reset(). But add a TODO if this is intended. Note: Stoney Ridge is using CF9 for the actual reset but the configuration for a cold reset doesn't use the usual full reset bit but some other mechanism. Change-Id: Id33eda676d79529db759b85fa8e28386846e6fa4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-03soc/amd/stoneyridge: Add IOMMU supportMarc Jones
Enable the IOMMU in AGESA and copy the AGESA generated IVRS ACPI table. BUG=b:116196614 TEST=Check dmesg for AMD-Vi messages. Change-Id: I688d867c7bd4949a57b27c1b6a793c6a6e4a717a Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/28753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-28soc/amd/common/block/pi: Remove references to AmdLibRichard Spiegel
In preparation to remove AmdLib, remove all references to AmdLib.h in folder common/block/pi. BUG=b:112525011 TEST=Buildgrunt. Change-Id: I3530857b872d0cb5ed2e3f3a294cc50b45ff6969 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28737 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Charles Marslett <charles.marslett@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-24soc/amd/stoneyridge/romstage.c: Move STAPM code to SOC specificRichard Spiegel
STAPM programming was created inside function OemCustomizeInitEarly(). It should be SOC specific, and called by agesawrapper just before the call to OemCustomizeInitEarly(). BUG=b:116196626 TEST=build and boot grunt Change-Id: I8a2e51abda11a9d60a9057b38f2a484e1c8c9047 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28705 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-17soc/amd/common/block/pi/agesawarapper.c: Use find_image()Richard Spiegel
In preparation to removing AmdLib, replace function LibAmdLocateImage() with its ported version find_image(). BUG=b:112625809 TEST=Build and boot grunt. Change-Id: I75ddd55f7e3e7f2cd7914f97c99b62690ae70660 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28164 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-17soc/amd/common/block: Port vendorcode's LibAmdLocateImageRichard Spiegel
In preparation to removing AmdLib, function LibAmdLocateImage() has to be ported to be used by agesawrapper. The most important aspect of this porting is that it has to obey coreboot format, specifically 8 character tab and 80 characters max. This required breaking the function in 2 (to solve indentation) and rename some variables to shorter names. One important aspect was breaking (AMD_MODULE_HEADER*)(((AMD_IMAGE_HEADER *) CurrentPtr)->ModuleInfoOffset) into: image_ptr = (AMD_IMAGE_HEADER *) current_ptr; if (validate_image((void *)image_ptr->ModuleInfoOffset, and, within validate_image completed by: AMD_MODULE_HEADER *mod_ptr = (AMD_MODULE_HEADER *)module_chain; BUG=b:112625809 TEST=Build grunt, functionality tested in next commit. Change-Id: I0d1e8b966cf7606fdb15a95de5771f835f07b2bc Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-03soc/amd/common: Remove PSPP override settingMarc Jones
For some reason the PSPP setting was being overwritten in the common code. Remove the setting and allow the oem customize function to make the setting. BUG=b:112020107 TEST= build test Change-Id: If7f4511a71f725fedd60d33552656850e50d955d Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-02soc/amd/common: Change create_struct return valueKyösti Mälkki
Old return value was not used, and function body has die() in case of errors in allocation. Change-Id: I89b0e9c927d395ac6d27201e0b3a8658e9585187 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/27261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-02soc/amd/common: Fix agesawrapper CreateStruct callsKyösti Mälkki
When AllocationMethod == ByHost, buffer has to be provided by caller. Improve code symmetry, the named parameter is now always pointer to the struct. Change-Id: I2085f7d5d63ef96f4bd9d5194af099634c402820 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/27112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-06-28amd/common/pi: Remove AGESA support files from bootblockMarshall Dawson
The stoneyridge bootblock no longer makes AGESA calls. Remove the support files from the bootblock build. TEST=boot Grunt Change-Id: I14d2336d5fb766a1acf5e812337ae0ab3ca4a6c1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-28amd/common/pi: Remove obsolete heapmanager workaroundMarshall Dawson
Remove residual code that allowed successful building of the heapmanager code. Now that stoneyridge no longer makes AGESA calls in bootblock, it is safe to elimate the workaround. BUG=b:74518368 TEST=boot Grunt Change-Id: Ie169a691a177bcd8283c31c8188ce28bcbce82af Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-21soc/amd/common: Always set GetBiosCalloutKyösti Mälkki
The entire StdHeader field is really supposed to be forked from a template for each entry into the AGESA API. Current code assumes only Callout would be relevant, which is not quite the case. Change-Id: I0cc66d01d62fa8dc6bb7c9f9fab6fa4753827554 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/27111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-06-14src: Get rid of unneeded whitespaceElyes HAOUAS
Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14AGESA binaryPI: Drop tests for LATE_CBMEM_INITKyösti Mälkki
Change-Id: I4571e8b560559b3d7afe429eca8caa1512e244a8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-13amd/pi: Add AgesaHeapRebase calloutMarshall Dawson
Implement an optional callout for AgesaHeapRebase which allows AGESA to override any internal hardcoded heap addresses. Designate a region in CAR that may be used for pre-mem heap and return that address before DRAM is configured. After DRAM is up, the address in cbmem is returned. TEST=Boot grunt with patchstack and experimental blob BUG=b:74518368 Change-Id: Ieda202a6064302b21707bd7ddfabc132cd85ed45 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/25458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-13amd/pi: Add GetTempHeapBase calloutMarshall Dawson
Implement a new AGESA callout that may be used to find the correct temporary location in DRAM to store heap data. Near the end of AmdInitPost, AGESA migrates its heap from a CAR-based location to a temporary region. Once cbmem has been established, the heap will be relocated again in AmdInitEnv from the temp location to the final one. This patch does not materially affect the behavior of AGESA's heap management. It only puts coreboot in control of the location. Future work may refactor the copying. TEST=Boot grunt with patchstack and experimental blob BUG=b:74518368 Change-Id: Ibc5cc988e3e80d78f50cf0195e952b657141e570 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/26146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-04src/soc: Get rid of whitespace before tabElyes HAOUAS
Change-Id: Ia024fb418f02d90c38b9a35ff819c607b9ac4965 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-19cpu/x86: Add support to run function on single APSubrata Banik
This patch ensures that user can select a specific AP to run a function. BUG=b:74436746 BRANCH=none TEST=Able to run functions over APs with argument. Change-Id: Iff2f34900ce2a96ef6ff0779b651f25ebfc739ad Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26034 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14cpu/x86: Add support to run function with argument over APsSubrata Banik
This patch ensures that user can pass a function with given argument list to execute over APs. BUG=b:74436746 BRANCH=none TEST=Able to run functions over APs with argument. Change-Id: I668b36752f6b21cb99cd1416c385d53e96117213 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-14grunt: use stage cache when waking from S3Raul E Rangel
BUG=b:79154155 TEST=built and tested on grunt 31 entries total: 0:1st timestamp 20,917 900:calling AmdInitReset 87,525 (66,608) 901:back from AmdInitReset 98,318 (10,793) 902:calling AmdInitEarly 99,165 (847) 903:back from AmdInitEarly 139,619 (40,454) 5:start of verified boot 156,301 (16,682) 503:starting to initialize TPM 156,697 (396) 504:finished TPM initialization 186,107 (29,410) 505:starting to verify keyblock/preamble (RSA) 187,316 (1,209) 506:finished verifying keyblock/preamble (RSA) 208,000 (20,684) 507:starting to verify body (load+SHA2+RSA) 208,108 (108) 508:finished loading body (ignore for x86) 273,238 (65,130) 509:finished calculating body hash (SHA2) 290,364 (17,126) 510:finished verifying body signature (RSA) 294,236 (3,872) 511:starting TPM PCR extend 295,071 (835) 512:finished TPM PCR extend 320,512 (25,441) 513:starting locking TPM 320,514 (2) 514:finished locking TPM 332,081 (11,567) 6:end of verified boot 332,083 (2) 13:starting to load romstage 332,187 (104) 4:end of romstage 395,559 (63,372) 10:start of ramstage 395,999 (440) 916:calling AmdS3LateRestore 396,135 (136) 917:back from AmdS3LateRestore 428,066 (31,931) 30:device enumeration 428,087 (21) 40:device configuration 434,640 (6,553) 50:device enable 438,185 (3,545) 60:device initialization 439,565 (1,380) 70:device setup done 453,326 (13,761) 918:calling AmdS3FinalRestore 454,363 (1,037) 919:back from AmdS3FinalRestore 455,520 (1,157) 98:ACPI wake jump 467,541 (12,021) Total Time: 446,624 Change-Id: I326e81d3c987130e258c616c7c66dd82ddc0d942 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/26219 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08amd/common/pi: Insert missing newline in printkMarshall Dawson
Add a newline to the unsupported callout message. Change-Id: I9bfff0ed920843f6c0818b51ee0046366f2a5c8d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/26144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-04-24soc/amd/common/block/pi/amd_late_init.c: Fix illegal memory accessRichard Spiegel
Found-by: Coverity (CID 1387031: Memory - illegal accesses (BUFFER_SIZE_WARNING)). Calling strncpy with a maximum size argument of 19 bytes on destination array "dimm->module_part_number" of size 19 bytes might leave the destination string unterminated. Fix the size parameter. BUG=b:76202696 TEST=Build and boot kahlee, using special debug code to see the output strings, which was later removed. Change-Id: I18fa5e9c73401575441b6810f1db80d11666368c Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-24compiler.h: add __weak macroAaron Durbin
Instead of writing out '__attribute__((weak))' use a shorter form. Change-Id: If418a1d55052780077febd2d8f2089021f414b91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-19soc/amd/common/block/pi/heapmanager.c: Simplify codeRichard Spiegel
There are sections of code that are almost identical and they can be converted to auxiliary procedures. For allocating heap, 3 sizes (the buffer size of currently being examined node, the buffer size of the current best fit node and the minimum size for a buffer that will need to be split if selected as the best fit) are used often so they could be stored in temporary variables. These 2 changes will make code shorter, with less indentation problems and overall easier to read. The actual logic of the code is not changed. BUG=b:77940747 TEST=Build and boot grunt. Change-Id: Ib4c69981eab7452228ccae9ed9bc288c8baceffe Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25703 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-12include/memory_info.h: Change serial number field from 5 bytes to 4Raul E Rangel
dimm_info.serial had a strange contract. The SPD spec defines a 4 byte serial number. dimm_info.serial required a 4 character ascii string with a null terminator. This change makes the serial field so it matches the SPD spec. smbios.c will then translate the byte array into hex and set it on the smbios table. There were only two callers that set the serial number: * haswell/raminit.c: already does a memcpy(serial, spd->serial, 4), so it already matches the new contract. * amd_late_init.c: Previously copied the last 4 characters. Requires decoding the serial number into a byte array. google/cyan/spd/spd.c: This could be updated to pass the serial number, but it uses a hard coded spd.bin. Testing this on grunt, dmidecode now shows the full serial number: Serial Number: 00000000 BUG=b:65403853 TEST=tested on grunt Change-Id: Ifc58ad9ea4cdd2abe06a170a39b1f32680e7b299 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/25343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-11soc/amd: Fix generating SMBIOS Type 17Raul E Rangel
The converter was setting SMBIOS values when dimm_info expects SPD values. dmidecode now shows the following: Memory Device Array Handle: 0x0000 Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 8192 MB Form Factor: SODIMM Set: None Locator: Channel-0-DIMM-0 Bank Locator: BANK 0 Type: DDR4 Type Detail: Synchronous Speed: 933 MT/s Manufacturer: Hynix/Hyundai Serial Number: 00000000 Asset Tag: Not Specified Part Number: HMAA51S6AMR6N-UH Rank: 1 Configured Clock Speed: 933 MT/s Minimum Voltage: Unknown Maximum Voltage: Unknown Configured Voltage: Unknown Example debug output: AGESA TYPE 17 DMI INFO: Handle: 1 TotalWidth: 64 DataWidth: 64 MemorySize: 8192 DeviceSet: 0 Speed: 1200 ManufacturerIdCode: 44416 Attributes: 1 ExtSize: 0 ConfigSpeed: 933 MemoryType: 0x1a FormFactor: 0xd DeviceLocator: DIMM 0 BankLocator: CHANNEL A SerialNumber(8): ' 00000000' PartNumber(20): 'HMAA51S6AMR6N-UH ' CBMEM_ID_MEMINFO: dimm_size: 8192 ddr_type: 0x1a ddr_frequency: 933 rank_per_dimm: 1 channel_num: 0 dimm_num: 0 bank_locator: 0 mod_id: 44416 mod_type: 0x4 bus_width: 3 serial: 0x00000000 module_part_number(18): 'HMAA51S6AMR6N-UH ' The serial number we get from AGESA (at least on my board) is always 00000000. I'm assuming this is because the SPD info is compiled in. `mosys memory spd print all` is still failing though. I will look into that next. BUG=b:65403853 BRANCH=dimm-info TEST=Test output above Change-Id: I076bc3f965f81a9374c8976da48c7fdce014dc0c Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/25304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-10soc/amd: Add "halt this AP" callback to romstageRichard Spiegel
As part of moving AGESA calls from bootblock to romstage, callback function AGESA_HALT_THIS_AP must be available at romstage. BUG=b:74236170 TEST=Build and boot grunt, actual test will be performed at a later patch. Change-Id: I0992b2de5856881c19191ec4f637168727686524 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25527 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-06amd/common/block/pi: Make agesa_heap_base() staticMarshall Dawson
Convert agesa_heap_base() to static since it's unused outside of heapmanager.c. Change-Id: I3ee162985ca1ea36461ea413416d98451a700f8c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/25457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-03-23soc/amd: Print dimm_info and TYPE17_DMI_INFO to help debug incorrect valuesRaul E Rangel
Example output: AGESA TYPE 17 DMI INFO: Handle: 1 TotalWidth: 64 DataWidth: 64 MemorySize: 8192 DeviceSet: 0 Speed: 1200 ManufacturerIdCode: 44416 Attributes: 1 ExtSize: 0 ConfigSpeed: 933 MemoryType: 0x1a FormFactor: 0xd DeviceLocator: DIMM 0 BankLocator: CHANNEL A SerialNumber(8): 00000000 PartNumber(20): HMAA51S6AMR6N-UH CBMEM_ID_MEMINFO: dimm_size: 0 ddr_type: 0x1a ddr_frequency: 1200 rank_per_dimm: 1 channel_num: 0 dimm_num: 0 bank_locator: 0 mod_id: 44416 mod_type: 0x1a bus_width: 64 serial(4): 0000 module_part_number(23): HMAA51S6AMR6N-UH ��@ dimm_size, mod_type, bus_width need to be updated so they return the correct values. module_part_number is missing a null terminator due to the AGESA part number being larger than the dimm_info buffer. Example dmidecode output: Memory Device Array Handle: 0x0000 Error Information Handle: Not Provided Total Width: 8 bits Data Width: 8 bits Size: No Module Installed Form Factor: Unknown Set: None Locator: Channel-0-DIMM-0 Bank Locator: BANK 0 Type: DDR4 Type Detail: Synchronous Speed: 1200 MT/s Manufacturer: Hynix/Hyundai Serial Number: 0000 Asset Tag: Not Specified Part Number: HMAA51S6AMR6N-UH Rank: 1 Configured Clock Speed: 1200 MT/s Minimum Voltage: Unknown Maximum Voltage: Unknown Configured Voltage: Unknown To enable the output set CONFIG_DEBUG_RAM_SETUP. The Kconfig change is required in order to enable CONFIG_DEBUG_RAM_SETUP, otherwise it's not a valid option. BUG=b:65403853 TEST=Test output shown above Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5eac00b9400056357915761287770a400b3f9f8b Reviewed-on: https://review.coreboot.org/25303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-16soc/amd/stoneyridge: Create a HALT_THIS_AP calloutRichard Spiegel
It was required for all cores use the same CAR teardown function (exit_car.S and gcccar.inc). AGESA has already been modified to do the AP to do the call out. Create assembly code to call chipset_teardown_car and then enter an endless loop with halt instruction. Then create the call out that will call this new assembly code. BUG=b:70338633 AGESA COMMIT=3313d277 TEST=Created a debug version of AGESA that would print the returned status of HALT_THIS_AP. Build code without the fix, see the return. Build code with the fix, see that there's no return. Change-Id: I05ee405812211d93dfdbdc5ee7d9978c2eb585e1 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/24999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-26soc/amd/common: Save the UMA settings from AGESAMarc Jones
Save the UMA base and size settings returned by AGESA in amdinitpost(); Change-Id: Id96cc65582118ad41d397b1a600cab1615676a55 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/23818 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-13 21:27:38 +0000