coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2017-10-02	soc/amd/common: Add framework for missing AGESA callouts	Martin Roth
2017-09-30	soc/amd/common: Add included directory	Marshall Dawson
2017-09-27	soc/amd/stoneyridge: Revert CAR teardown wbinvd	Marshall Dawson
2017-09-27	soc/amd/stoneyridge: Add postcar stage	Marshall Dawson
2017-09-27	amd/stoneyridge: Put AGESA heap into cbmem	Marshall Dawson
2017-09-27	soc/amd/common: Clean up GetHeapBase function	Marshall Dawson
2017-09-26	AGESA: Avoid cpuRegisters.h include	Kyösti Mälkki
2017-08-28	soc/amd: Standardize guards on header files	Martin Roth
2017-08-14	stoneyridge: Rename hudson to southbridge	Marc Jones
2017-07-27	soc/amd/common: Convert to C_ENVIRONMENT_BOOTBLOCK	Marshall Dawson
2017-07-13	Rename __attribute__((packed)) --> __packed	Stefan Reinauer
2017-07-11	binaryPI: Define AGESA blob in CBFS as Kconfig string	Kyösti Mälkki
2017-07-02	soc/amd/common: Add initial support for AMD PSP	Marshall Dawson
2017-06-27	soc/amd/common: Fix most checkpatch errors	Marshall Dawson
2017-06-27	vendorcode/amd: Unify Porting.h across all targets	Stefan Reinauer
2017-06-26	soc/amd/stoneyridge: Add northbridge support	Marc Jones
2017-06-26	soc/amd/stoneyridge: Add CPU files	Marc Jones
2017-06-26	soc: Add AMD Stoney Ridge southbridge code	Marc Jones