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path: root/src/soc/amd/picasso/include
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2021-05-19soc/amd/picasso: move gpp_clk_req_setting definition to chip.hFelix Held
Since this enum is only used for the devicetree settings and not for the hardware itself, move it from the southbridge header to the chip one. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0907fc5cba9315fec5fabff67d279c6d95d1c9f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54684 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06soc/amd/{picasso/common}: Move populate_pirq_data prototype to commonRaul E Rangel
This method signature will also be used by cezanne, so move it to common. BUG=b:184766519 TEST=Build picasso Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I421bdad51776278f83148174e6f72bdc38249e54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-29soc/amd/picasso: move PSP_SRAM addrs to separate headerKangheui Won
These addresses will be changed in cezanne. Before start working on cezanne, move these out to separate header as a clean-up. TEST=emerge-zork coreboot Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I2499281d250aae701f86bfcc87c7681e5b684b6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-29soc/amd/common/acp: Move Audio Co-processor driver to commonKarthikeyan Ramasubramanian
Audio Co-processor driver is similar for both Picasso and Cezanne SoCs. Hence move it to the common location. BUG=None. TEST=Builds Dalboz, Trembyle, Vilboz, Mandolin and Bilby mainboards. Change-Id: I91470ff68d1c183df9a2927d71b03371b535186a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-23soc/amd/picasso: clean up Kconfig and headerKangheui Won
Clean up Kconfig and psp_trasfer.h files before copying over to cezanne. TEST=build, flash and boot on jelboz360 Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Ib370d93e23c15a2fe4c46051ed3647d2d067bb10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52563 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23amd/vboot: remove bl_syscall_public.h from includeKangheui Won
bl_syscall_public.h is a header file for PSP app, but was used for x86 code to get the definition of PSP_INFO. Move the definition into psp_transfer.h and do not include bl_syscall_public.h from x86 code. BUG=none TEST=build psp_verstage on zork BRANCH=none Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I0fe011652a47d0ba2939dc31ee3b83f0718a61dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/52537 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-14soc/amd/piasso/fch: use common pm_set_power_failure_state functionalityFelix Held
The functionality to restore the previous power state after power was lost that could previously be enabled by selecting MAINBOARD_POWER_RESTORE in the mainboard's Kconfig can now be achieved by selecting POWER_STATE_PREVIOUS_AFTER_FAILURE in the mainboard's Kconfig instead. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iab9578ebea89651dc2389bf6ca93ca3f3507eb47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-29soc/amd/picasso: factor out UPD-M configuration from romstageFelix Held
Move the parts of romstage.c that populate the UPD-M data structure to the newly created fsp_m_params.c file. Since platform_fsp_memory_init_params_cb gets called from the FSP driver and not directly from car_stage_entry the two code parts in romstage.c weren't directly interacting. Since soc/romstage.h only contains the mainboard_updm_update function prototype, rename it to soc/fsp.h. This patch also removes a few unused includes. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I52c21f13520dbdfab37587d17b3a8a3b1a780f36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-29soc/amd: move PM_RST_CTRL1 register definition to common acpimmio headerFelix Held
TEST=Verified that this register and the defined bits exist in Cezanne, Picasso, Stoneyridge, Bolton and SB800. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I32d1d577b05edab006981516a5aefd822e7b984a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-22soc/amd/common/block/i2c: Move SoC agnostic parts into commonKarthikeyan Ramasubramanian
The logic behind I2C bus initialization, I2C MMIO base address getter and setter, I2C bus ACPI name resolution are identical for all the AMD SoCs. Hence moving all the SoC agnotic parts of the driver into the common driver and just configure the SoC specific parts into individual I2C drivers. BUG=None TEST=Build Dalboz and Grunt. Boot to OS in Dalboz. Ensure that the I2C peripherals are detected as earlier in Dalboz. Verify some I2C peripheral functionality like trackpad and touchscreen. Change-Id: Ic9c99ec769d7d8ad7e1e566fdf42a5206657183d Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Suggested-by: Kyosti Malkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51509 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22soc/amd/common: Introduce I2C driver common to all AMD SoCsKarthikeyan Ramasubramanian
I2C driver is replicated in each generation of AMD SoCs. Introduce a common I2C driver that can be used across all the AMD SoCs. To begin with, peripheral reset functionality is moved into this common driver. SoC specific I2C driver passes the SCL pin configuration in order for the common driver to reset the peripherals. More functionality can be moved here in subsequent changes. Also sb_reset_i2c_slaves() is renamed as sb_reset_i2c_peripherals() as an effort towards using inclusive language. BUG=None TEST=Build Dalboz and Grunt. Boot to OS in Dalboz. Ensure that the I2C peripherals are detected as earlier in Dalboz. localhost ~ # i2cdetect -y 0 Warning: Can't use SMBus Quick Write command, will skip some addresses 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 10: 20: 30: -- -- -- -- -- -- -- -- 40: 50: 50 51 -- -- -- -- -- -- 58 59 -- -- -- -- -- -- 60: 70: localhost ~ # i2cdetect -y 1 Warning: Can't use SMBus Quick Write command, will skip some addresses 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 10: 20: 30: -- -- -- -- -- -- -- -- 40: 50: UU -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: 70: Change-Id: I9f735dcfe8375abdc88ff06e8c4f8a6b741bc085 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Suggested-by: Kyosti Malkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-12soc/amd/common/block/smu: rename mailbox register definesFelix Held
Since we have the SMN access block now, rename the SMU mailbox interface registers to clarify that those are in the SMN register space. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic5b7093f99eabd3c29610072b186ed156f335bd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-11soc/amd: move warm reset flag function prototypes to common codeFelix Held
Even though the implementation is different on Stoneyridge compared to Picasso and Cezanne, the function prototypes are identical, so move them to the AMD SoC common reset header file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8d3a3a9ea568ea18658c49612efabdbe36d5f957 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-10soc/amd/picasso: Allow GPIO defines to be used in ASLMathew King
BUG=b:182269526 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Ib33a46a6eead84eaff2c4ac320800b7993f5c3f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-10mb/google/zork: add UPDM updating function before runing FSP-MChris Wang
Add the UPD updating hook in early stage for customization. BUG=b:117719313 BRANCH=zork TEST=build,check the hook function been executed. Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I4954a438a51b29b086015624127e651fd06f971b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51181 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-06soc/amd/picasso: move APOB NV cache to common codeFelix Held
Also rename mrc_cache to apob_cache. BUG=b:181766974 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4877b05443452c7409006c1656e9d574e93150a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-18soc/amd/picasso/chip: make soc_acpi_name staticFelix Held
This function isn't used outside of the same compilation unit. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I332046341bc7a5a499355f2147296e8c09d7e0ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/50817 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-17soc/amd/*/iomap: remove unused ACPI_SMI_CTL_PORTFelix Held
This was replaced by APM_CNT defined in src/include/cpu/x86/smm.h, so remove the now unused definitions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibd25dcdb57de14fe42352f01067cedca53712d56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-02-14soc/amd/picasso/data_fabric: factor out common MMIO register definesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I663a73308d33f48c6b945007f3eaac84d4712f59 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50639 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14soc/amd/picasso: move data_fabric_read32 to common codeFelix Held
The exact same mechanism is used on Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3179d8ec35efa29f9bc66854c3690b389d980bba Reviewed-on: https://review.coreboot.org/c/coreboot/+/50619 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12soc/amd: Move southbridge_write_acpi_tablesRaul E Rangel
This is common between all the chipsets. It's also required by common/block/lpc/lpc.c. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I361dfabfe0c04667a2c112955133831a985d5cc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-11mainboards: Drop PWRS from GNVSKyösti Mälkki
Initialize variable to 1 to indicate AC power supply. If platform has EC it will set this correctly based on whether plugged on the charger or not. Change-Id: I3f834cf7563b9e512fcab34cdb7a27a9f0fd31c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49352 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10soc/amd/picasso: Add SPI registersRaul E Rangel
The picasso SPI registers are different than the ones defined in amdblocks/lpc.h. The BASE_ALIGNMENT has changed and the PSP_SPI_MMIO_SEL bit has been added. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0b5a0c88c6dbb95cdbc62b949a7d30bfad1fa725 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-09Revert "soc/amd/picasso: Change GPIO _HID to AMDI0030"Martin Roth
This reverts commit 75f6ab35ffefec72e343175686d7ef45b30b0939. Reason for revert: The 5.4 Linux kernel is not configured for AMDI0030. This causes an issue where the WP pin is not recognized. BUG=b:179320024 TEST=WP pin shows up properly in crossystem after reverting this change. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I0850fd085b5ee70522752633900f69d4d3732321 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50052 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-09soc/amd/picasso/cpu: move get_cpu_count to common codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0690787f492d764a20a4219822eb10fb5cd86de0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-08soc/amd/picasso/iomap: change ACPI_CPU_CONTROL to match AGESAFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I80e11d9792ee4138cb376ebbe0438dc304b54527 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50288 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-07soc/amd/picasso: Move memmap_early_dram to common blocksRaul E Rangel
We need the same functionality for cezanne. TEST=Boot ezknil Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0800c662bb473eb571c74e76a8247298f534b53f Reviewed-on: https://review.coreboot.org/c/coreboot/+/50337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-05soc/amd/picasso: remove PICASSO_ACPI_IO_BASE Kconfig optionFelix Held
This was the only I/O base address in Kconfig, no board changed it and if a board changed it, it needs to make sure that it won't overlap with other I/O resources, so just use the same value as constant in the define instead of the value from Kconfig. Also remove the PICASSO_ prefix from ACPI_IO_BASE. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7ea62f1101ddefa8785da92de5ba2aaf7945694a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-04soc/amd/picasso: Fix copy-paste error in macro definitionsAngel Pons
The `_MASK` macros should be using the corresponding `_SHIFT` macros. Change-Id: I78370e17d2396f77ab820771f93cf15957bcf674 Found-by: Coverity CID 1445928 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-04soc/amd/picasso: set GPE0_LIMIT to 32 and move definitions to registersFelix Held
Picasso has 32 configurable GPEs, not only 28. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia156e64e7a69764776f3af7597b680b8ddd4e650 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-02soc/amd/picasso/include/soc/southbridge: remove PM_USB_ENABLE definesFelix Held
This define was copied over from Stoneyridge, but isn't present on Picasso and newer. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ideb144c4bff441cf043a647b3f44a65691038eba Reviewed-on: https://review.coreboot.org/c/coreboot/+/50205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-01soc/amd: Drop PCNT from GNVSKyösti Mälkki
It's a static value that is neither referenced from SMI handler nor needs to be updated on S3 resume path. Change-Id: Iab2741242b0e2df8a0429ffaad270ce21882588c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-30soc/amd/piasso/data_fabric: rename data_fabric_read_reg32Felix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib1b4da8f5daac2bae5e54f213accda03e121297d Reviewed-on: https://review.coreboot.org/c/coreboot/+/50098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-01-29soc/amd/picasso/fch: replace southbridge prefix with fchFelix Held
Also move the fch_* functions in the header file in the order they get called. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9b6c6ad744b26f8488015c38a84d7e21c7d7687a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50093 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28soc/amd/picasso: allow USB_PD port setting overrideChris Wang
Allow to override the RFMUX setting if the board does not use PD chip. BUG=b:177389383 BRANCH=none TEST=Build; Check the USB_PD port been override. Change-Id: Idd559b67668846805005a6e00f5a84655310f348 Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49932 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25soc/amd/picasso: Change GPIO _HID to AMDI0030Raul E Rangel
This matches the _HID used in the picasso UEFI bios. BUG=none BRANCH=zork TEST=boot linux and verify peripherals still work Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ieb441696cbe67a772632990347c12d1d15cfaf13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-25soc/amd: Refactor ACPI power state and ELOGKyösti Mälkki
Change-Id: Ib7423c8d80355871393c377ebaffdfe2846d8852 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-23soc/amd: Rename chipset_state to chipset_power_stateKyösti Mälkki
To implement some common helpers for CBMEM_ID_POWER_STATE allocation use the same struct name as soc/intel. Change-Id: I5d2c06a2a7b4602374562197c99b0ad7bcf50afb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-18ACPI: Refactor ChromeOS specific ACPI GNVSKyösti Mälkki
The layout of GNVS has expectation for a fixed size array for chromeos_acpi_t. This allows us to reduce the exposure of <chromeos/gnvs.h>. If chromeos_acpi_t was the last entry in struct global_nvs padding at the end is also removed. If device_nvs_t exists, place a properly sized reserve for chromeos_acpi_t in the middle. Allocation from cbmem is adjusted such that it matches exactly the OperationRegion size defined inside the ASL. Change-Id: If234075e11335ce958ce136dd3fe162f7e5afdf7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-15soc/amd/picasso: Generate ACPI CRAT objects in cbJason Glenesk
Add code to collect all required information and generate ACPI CRAT table entries. Publish tables generated from cb, rather than use the tables created by FSP binary. BUG=b:155307433 TEST=Boot trembyle and compare coreboot generated tables with tables that FSP published previously. BRANCH=Zork Change-Id: If64fd624597b2ced014ba7f0332a6a48143c0e8c Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-14soc/amd/piasso/uart: move get_uart_base prototype to common code headerFelix Held
This will result in less code duplication when the common AMD SoC UART support gets used for more AMD SoCs. Change-Id: Id1786f32324de3e3947d792c599e2019705c5a85 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49373 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-14soc/amd/picasso: remove broken and unused legacy UART supportFelix Held
The UARTs in the Picasso SoC are memory mapped, but there is also some hardware support that isn't used by any board to make the UARTs behave like the ones found on legacy x86 machines from the 90s. In the MMIO mode the MMIO address of the UART controller is passed to the OS via ACPI. The OS expects the base clock of the UART controller to be 48MHz (see the cz_uart_desc struct in drivers/acpi/acpi_apd.c and drivers/tty/serial/8250/8250_dw.c in the Linux kernel) in this case. It is also possible to enable additional decodes from four 8 byte legacy I/O locations used for serial ports to the different UART controllers, which doesn't disable the MMIO access though. The legacy I/O-mapped serial ports are usually expected to have a base clock of 16*115200Hz which the hardware can also provide to the UART's baud rate generator. So there are two possible valid configurations to use the UARTs; either MMIO access in combination with a 48MHz base clock or the legacy I/O decode with a ~1.8MHz base clock. The existing code unconditionally generates ACPI objects for all enabled UARTs, so those shouldn't be put into legacy mode and switching the base clock to ~1.8MHz was only done in the case that the UART was used as coreboot console UART which still used the MMIO access, but the lower base clock. Since no board even selects this option and it's rather invasive to properly implement this feature, just drop the corresponding broken code. TEST=SoC UART console still works on Mandolin. Change-Id: I26fa8fdfc781b583ba56ac4dbcbbfb6100e84852 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reported-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49371 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-06soc/amd/picasso: Correctly populate the PCI interrupt line registerRaul E Rangel
The PCI interrupt line registers are used as a last resort if routing can't be fetched from either ACPI or the MPTable. This change correctly sets the registers. It overrides the pirq_data set by the mainboards since the routing is fixed in AGESA. BUG=b:170595019 TEST=Boot ezkinil with `pci=nomsi,noacpi amd_iommu=off noapic` Verified all PCI peripherals are still functional. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: If5d4d8f613c8d0fa9b43cefa804824681c3410d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-16soc/amd/picasso: Fix the typo in GPIO defineZheng Bao
Change-Id: I8c9eed5d0e320b02382c24304a44e51e89eb6ac5 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-15soc/amd/picasso/smi: add missing bits to GEVENT_MASKFelix Held
GEVENT_MASK should cover all GEVENT pins, but was missing SMITYPE_G_AGPIO9 and SMITYPE_G_AGPIO8. Change-Id: Ia676476e2d2cf468d82d6d90e9fc11d34f56f153 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-12-15soc/amd/common,picasso: Place some ENV_X86 guardsKyösti Mälkki
Base address symbols for ACPIMMIO banks that would not get assigned at runtime must not resolve at linker-stage either. The build of PSP-verstage should pass without the preprocessor macros that have x86-centric view of memory space. Change-Id: I3cb1b5a90023ebc4359835be716c5e3f9451df60 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-13soc/amd/*/include/spc/gpio: fix pin numbers in commentsFelix Held
Change-Id: I9e91f28659c49927aaa4c7cd67f73bb11258c27c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-11soc/amd/picasso: Add data fabric read helper functionJason Glenesk
Add new helper function to support reading a register from the data fabric. BUG=b:155307433 TEST=Boot trembyle with If64fd624597b2ced014ba7f0332a6a48143c0e8c and confirm read values match expected values. BRANCH=Zork Change-Id: If0dc72063fbb99efaeea3fccef16cc1b5b8526f1 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47726 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10soc/amd/picasso/reset: use port and bit defines from cf9_reset.hFelix Held
The register name and the name of one bit are slightly different, but have the same functionality. Change-Id: I025f1c7b2c7643afe245f2275ae6ef45e64b951a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48487 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09soc/amd/picasso,stoneyridge: drop unused BIOSRAM offset definesFelix Held
The two Socs don't use this functionality and biosram.c in the common code is the only place where those defines are used, but it doesn't include soc/iomap.h and has its own definitions instead. Change-Id: I973df4ab39a94e89ea2ed6ffb639c5a85b8df456 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-11 01:46:26 +0000