Age | Commit message (Collapse) | Author |
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* Introduce a measured boot mode into vboot.
* Add hook for stage measurements in prog_loader and cbfs.
* Implement and hook-up CRTM in vboot and check for suspend.
Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently this needlessly initializes the hardware in the both the
romstage and the bootblock, but it works.
Build option is renamed to USBDEBUG_IN_PRE_RAM to reflect the
use better, related support files can be built to pre-ram stages
regardless of usbdebug being enabled or not.
Tested on Google/peppy (adapted to C_ENVIRONMENT_BOOTBLOCK).
Change-Id: Ib77f2fc7f3d8fa524405601bae15cce9f76ffc6f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Makes vboot measured boot mode available for all boards.
* Increase Tegra210 and Rockchip3228 SRAM for
romstage/verstage.
* Add missing files for Intel apollolake and
AMD stoneyridge as TPM driver target.
Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Enable the IOMMU in AGESA and copy the AGESA generated IVRS ACPI table.
BUG=b:116196614
TEST=Check dmesg for AMD-Vi messages.
Change-Id: I688d867c7bd4949a57b27c1b6a793c6a6e4a717a
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/28753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Move the process of interrogating the Machine Check registers into
its own file. This rearranges source code in preparation of supporting
a Boot Error Record Table, which stoneyridge will use to report latent
MC errors to the OS.
BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack. Use test
data plus a failing Grunt system.
Change-Id: Ia3275e9135dc96ba4a717c9371f38843fa1e3e64
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Per AMD, the Integrated Micro Controller is not a supported feature of
the Stoney Ridge APU. Systems are expected to implement an external EC
for desired features. Remove all stoney IMC files and functions from
src/soc/amd/stoneyridge.
There are 2 "IMC bits" left (and used) that are not truly IMC. New BKDG
describe these bits, so a new patch will be released later to fix the
names and comment.
BUG=b:111780177
TEST=Build grunt and gardenia
Change-Id: I6a24e4c3f03d04713a030b884c611d9c64c4cb3a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27651
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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GPIO functions are required by the Grunt SMI handler.
Change-Id: Id729139b02c10bdd922b3df298f8f9feb1aff745
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/27485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The default interrupt control for GPIO pins within stoneyridge is for
edge triggered, high. However, sometimes these need to change, or maybe
the interrupt needs to be reported or delivered. This was the case of
platform grunt, where the interrupt related bits were being changed
afterwards. Ideally all the bits should be programmed through the same
procedure. Create several PAD_INT definitions (for general configuration,
for trigger configuration and for interrupt type configuration) and change
function sb_program_gpios() to accept the output from PAD_INT_XX and
program all the necessary bits while keeping compatibility with other
PAD_XX definitions.
BUG=b:72875858
TEST=Add code to report GPIO and interrupt configuration, build grunt and
record a baseline. Add new code, rebuild grunt and record a test output.
Compare baseline against test, there should be no change in GPIO or
interrupt programming.
Remove code that reports GPIO/interrupt configuration.
Change-Id: I3457543bdf64ec757fd82df53c83fdc1d03c1f22
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Now that we have SPI flash writes working, we can support
VBOOT_VBNV_CMOS_BACKUP_TO_FLASH. This requires the mainboard to reserve
the area in FMAP.
BUG=b:77347873
TEST=Manually clear CMOS and check coreboot restores VBNV from flash.
Change-Id: I488dbfc4c200f5100374d47feb0a0522e6a60e88
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/25842
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As part of moving AGESA calls from bootblock to romstage, create
infrastructure to pass a pointer to the AP cores, so they can jump directly
to romstage.
BUG=b:74236170
TEST=Build and boot grunt, actual test will be performed at a later patch.
Change-Id: If716d1c1970746f2ad90ef71ae9062c99f219897
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add a function to configure interrupt settings for a GPIO. This does
not currently configure GEVENT signals.
The second function returns the GPIO interrupt status and clears the
flag if set.
BUG=b:72838769
BRANCH=none
TEST=Update and test interrupt settings for GPIO_9 on grunt
Change-Id: I1addd3abcb6a57d916b1c93480bacb0450abddf2
Signed-off-by: Chris Ching <chingcodes@chromium.org>
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Move the remaining model_15_init.c functionality to cpu.c, making it
similar to other soc implementations.
Change-Id: Ic8c62b09209fcdaa50ff8ffc7773ef155f979a1b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23724
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Delay making TSEG valid until the end of POST. After the CPU setup,
there are times where coreboot needs to access the SMRAM from outside
of SMM. Also relocate locking of the SMM settings from the CPU init
to the end of POST (or just before resuming).
Change-Id: I70b7e33e7045d397e41f571caff6a2acbb64eaab
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The scratch registers in northbridge used for storing the top of
cacheable memory are volatile. Use the BiosRam storage in the FCH
instead.
TEST=Suspend and resume Kahlee with complete S3 patch stack
BUG=b:69614064
Change-Id: Ieb3cfd173c70bf899a6391d62d1df87b38485f30
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The TSC has been observed to be ticking at a non-constant rate
in early boot. The root cause is still not known, but this
misbehavior necessitates an alternative monotonic timer source.
Use the perf TSC which ticks at 100 MHz. This also means the
timestamp table is not accurate as well. Root cause of TSC rate
instability needs to be resolved in order to fix that.
BUG=b:72170796
Change-Id: Ie052169868a9d9f25f8cc0ce8dd8251b560e671f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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BUG=b:69416132
BRANCH=none
TEST=make
Change-Id: Id940af917c9525aba7bc25eea0821f5f36a36653
Signed-off-by: Chris Ching <chingcodes@chromium.org>
Reviewed-on: https://review.coreboot.org/22959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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All preparation done, early_setup.c now useless. Delete early_setup.c,
BUG=b:64033893
TEST=None.
Change-Id: Ibe75a2d5cc46641e9d0af462a8a0ba5bb7a0f9c3
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22569
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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In preparation to deleting early_setup,c, transfer all functions except
those related to wide IO to southbridge.c.
BUG=b:64033893
TEST=Build and boot to OS.
Change-Id: Ibe1d87cb3e0eb3e8ed4d2dc2adbddf2e13557c9e
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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- Move #defines to soc/northbridge.h, add other reset definitions to
soc/southbridge.h.
- Clean up file to use definitions instead of magic numbers.
- Add do_soft_reset()
BUG=b:69224851
TEST=Build gardenia; Build & boot Kahlee
Change-Id: I0cc4c04b53b7fec38d45e962ff1292d8c717269c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22439
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Add a mainboard function call to write the AGESA SPD buffer.
Removes the unneccesary dimm_spd.c file.
BUG=b:67845441
Change-Id: Id42622008b49b4559e648a7fa1bfd9f26e1f56a4
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Remove ugly camel case in the soc/amd/common and Stoney Ridge
SPD files and functions. Update the related mainboards.
Also, remove a unreferenced function prototype, smbus_readSpd().
Change-Id: I51045b6621f0708d61a570acbdcb4e6522baa1ea
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add more definitions for the controller registers and fields. Add
source that is adapted from hudson and updated for Stoney Ridge.
This was tested with follow-on patches that write S3 data to flash.
BUG=b:68992021
Change-Id: I61d64cfdb4fce11c068113680da7ba6a199d6893
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Change-Id: I23882ad8cd93fbc25acd8a07eca6a78b6bafc191
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Stoney Ridge supports two different sets of SMU firmware, one for
either fanless OPNs and one for fanned.
Add a Kconfig mechanism to select the proper set and add the blobs
into cbfs.
BUG=b:66339938
Change-Id: I8510823e2232b74ec6fe001cc28953f53b2aa520
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Move the two functions in fixme.c to places where they make more sense.
Coincidentally fix the todo in amd_initcpuio() and use bsp_topmem()
instead of explicitely reading the MSR.
BUG=b:62241048
Change-Id: Ica80b92f48788314ad290ccf72e6847fb6d039c3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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There was no reason to have the AGESA callout tables in each mainboard,
so move them to soc/amd/common.
Move chip specific functions into the stoneyridge directory:
- agesa_fch_initreset
- agesa_fch_initenv
- agesa_ReadSpd
Combine agesa_ReadSpd and agesa_ReadSpd_from_cbfs, and figure out which
to use.
Soldered-down memory still needs to be supported in a future commit, as
stoney supports both DDR3 & DDR4. A bug has been filed for support for
the upcoming Grunt platform.
BUG=b:67209686
TEST=Build and boot on Kahlee
Change-Id: Ife9bd90be9eb0ce0a7ce41d75cfef979b11e640b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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- Don't force the selection of placing the firmware outside of cbfs
when using vboot.
- Set a prompt to allow the option of placing it outside of cbfs.
- Leave all Kconfig defaults the same.
- Place the AMD firmware directory table in the specified location
even when using the 'outside of cbfs" option.
- Print where the firmware is being placed when placing it outside
of cbfs.
BUG=b:65484600
TEST=Assign PSP firmware location, build & test. Firmware shows up
inside CBFS. Set 'outside of cbfs' option, verify firmware gets
written to the correct location.
Change-Id: Ia8258b5c2ecfaaa42d623e3376ec3233115aed58
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21867
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The amdfwtool now outputs firmware that is correctly built for the
new location.
BUG=b:65484600
TEST=Assign PSP firmware location, build & test.
Change-Id: Ifa2e99ea031fc0d9f165ae44ff6b1afef369eb28
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Allow the AMD FW directory to be placed at one of the alternative
locations within the ROM.
BUG=b:65484600
TEST=Assign PSP firmware location, build & test.
Change-Id: I9c95b9805c60ab6204750f7929049c7382e0c6cd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Pull all pm_read and write, smi_read and write variants into a single
file.
Change-Id: I87d17361f923a60c95ab66e150445a6a0431b772
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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This corrects a build error when a developer needs DEBUG_SMM and one
of the APU's internal UARTs is used.
Change-Id: Ie1962e969a8cb93eefc0b86bf4062752580e5acd
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21740
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Stoney Ridge always now selects HAVE_SMI_HANDLER so it is pointless
to use the variable in Makefile.inc. Make all files built into smm
unconditional.
Change-Id: I4ea89d7bce83a99328c58897a4098debacd86d66
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Insert a postcar stage for Stoney Ridge and move romstage's CAR
teardown there.
The AMD cache-as-ram teardown procedure currently uses a wbinvd
instruction to send CAR contents to DRAM backing. This allows
preserving stack contents and CAR globals after the teardown
happens, but likely results in memory corruption during S3 resume.
Due to the current base of the DCACHE region, reverting to an
invd instruction will break the detection mechanism for CAR
migrated variables. Using postcar avoids this problem.
The current behavior of AGESA is to set up all cores' MTRRs during
the AmdInitPost() entry point. This implementation takes control
back and causes postcar's _start to clear all settings and set
attributes only for the BIOS flash device, TSEG, and enough space
below cbmem_top to load and run ramstage.
BUG=b:64768556
Change-Id: I1045446655b81b806d75903d75288ab17b5e77d1
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change the Stoney Ridge SOC to a more modern method for setting up
the multiple cores.
Add a new cpu.c file for most of the processor initiliazation. Build
mp_ops with the necessary callbacks. Note also that this patch removes
cpu_bus_scan. Rather than manually find CPUs and add them to the
devicetree, allow this to be done automatically in the generic
mp_init.c file.
SMM information is left blank in mp_ops to avoid having mp_init.c
install a handler at this time. A later patch will add TSEG SMM
capabilities for the APU.
This patch also contains a hack to mask the behavior of AGESA which
configures the MTRRs and Tom2ForceMemTypeWB coming out of AmdInitPost.
The hack immediately changes all WB variable MTRRs, on the BSP, to UC
so that all writes to memory space will make it to the DRAM.
BUG=b:66200075
Change-Id: Ie54295cb00c6835947456e8818a289b7eb260914
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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There's an occasional issue on machines which use CMOS for their
vbnv storage. The machine that just powers up from complete G3
would have had their RTC rail not held up. The contents of vbnv
in CMOS could pass the crc8 though the values could be bad. In
order to fix this introduce two functions:
1. vbnv_init_cmos()
2. vbnv_cmos_failed()
At the start of vboot the CMOS is queried for failure. If there
is a failure indicated then the vbnv data is restored from flash
backup or reset to known values when there is no flash backup.
BUG=b:63054105
Change-Id: I8bd6f28f64a116b84a08ce4779cd4dc73c0f2f3d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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- Get rid of CONFIG_ prefix from variables that don't come from Kconfig.
- Remove 2nd set of variables that are duplicates of the first set.
- Delete duplicate set of Prerequisites
Change-Id: I194b4c790b3e35353d480d34b60507a00f10ef11
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21451
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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- The SMU firmware used to be named *.sbin, now is named *.csbin.
Update the makefile so that the files can be named as they are
delivered and don't have to be renamed.
- Add a Kconfig option to allow the secure os binaries to be excluded.
BUG=b:64932297
TEST=Build with old and new firmware, verify file sizes.
Change-Id: I3091f8af126159488c3c398a6dc881fa05039cff
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Simplify funciton names and remove reference to hudson in stoneyridge.
The southbridge in Stoney Ridge is Kern and hudson naming is
no longer accurate.
BUG=b:62200157
BRANCH=none
TEST=Build and booted on Kahlee.
Change-Id: Ide7a72dae69b881997101f1e37a1ac739901744d
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20912
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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A mainboard may access GPIO in romstage.
Change-Id: Id380c6570943ce2a0bf6112d62cc91aeae283fcf
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add ACPI asl for global non-volatile storage (GNVS).
Change-Id: I9ecab92181bfe60e7b6c6e91ffb9fa843345352f
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/20275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Remove the unused support code from the old multi-device hudson
SD controller. The binaryPI blob contains the correct steps
for setting up SD and the public BKDG doesn't completely document
the controller.
The sd.c file was using device IDs not associated with the Stoney
Ridge APU. The hudson_enable() code removed was also looking for
incorrect device IDs and the PM_MANUAL_RESET register doesn't
behave as the source indicates.
The SD default settings may be overridden. Future improvements
may include a few Kconfig options and a weak call to the mainboard
for overriding additional defaults.
BUG=chrome-os-partner:62580062
Change-Id: I7dbd70320740e8a05e6bf16af125d67012f20674
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add Kconfig selects for vboot and update the makefile to pick up
files to be used in verstage.
Change-Id: If5c439a330d687156006aec2ebaea18ff2c96b3e
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19756
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add dedicated CAR setup and teardown functions and Kconfig
options to force their inclusion into the build. The .S files
are mostly duplicated code from the old cache_as_ram.inc file.
The .S files use global proc names in anticipation for use with
the Kconfig symbols C_ENVIRONMENT_BOOTBLOCK and POSTCAR_STAGE.
Move the mainboard romstage functionality into the soc directory
and change the function name to be compatible with the call
from assembly_entry.S. Drop the BIST check like other devices.
Move InitReset and InitEarly to bootblock. These AGESA entry
points set some default settings, and release/recapture the
AP cores. There are currently some early dependencies on
InitReset. Future work should include:
* Pull the necessary functionality from InitReset into bootblock
* Move InitReset and InitEarly to car_stage_entry() and out of
bootblock
- Add a mechanism for the BSP to give the APs an address
to call and skip most of bootblock and verstage (when
available) (1)
- Reunify BiosCallOuts.c and OemCustomize.c
(1) During the InitReset call, the BSP enables the APs by setting
core enable bits in F18F0x1DC and APs begin fetching/executing
from the reset vector. The BSP waits for all APs to also
reach InitReset, where they enter an endless loop. The BSP
sends a command to them to execute a HLT instruction and the
BSP eventually returns from InitReset. The goal would be to
preserve this process but prevent APs from rerunning early
code.
Change-Id: I811c7ef875b980874f3c4b1f234f969ae5618c44
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Use the TSC for the Stoney Ridge monotonic timer. Modern AMD
CPUs have invariant timestamp counters. This patch brings the
feature more in line with other devices and allows the use of
typical monotonic timer functions.
BUG=chrome-os-partner:62578062
Change-Id: I07b05fbc7cdea54a45daac01954284a9fd67e42f
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Remove IDE from the Stoney Ridge source. This APU doesn't have
an IDE controller. The support was left over from pi/hudson.
BUG=chrome-os-partner:62580062
Change-Id: I7316c113a7464089ccfbea6b6cf69787940b9e97
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Remove the pcie.c file. Historically PCIe lanes have been
available from the Gfx and/or the FCH. The integrated FCH in
this APU has no PCIe available.
BUG=chrome-os-partner:62580062
Change-Id: Ie89383dadfaa57c5a6d185e74551ae50ac8d9778
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The Stoney Ridge does not contain this bridge like some of the older
Hudson FCHs. Remove this support from the source.
This moves the Stoney Ridge IRQ setup to the southbridge file, hudson.c.
BUG=chrome-os-partner:62580062
Change-Id: I8f974ba76b8c20f4335dd8872eaf4b8172188ee2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Copy northbridge files from northbridge/amd/pi/00670F00
to soc/amd/stoneyridge and soc/amd/common.
Changes:
- update chip_ops and device_ops
- remove multi-node support
- clean up Kconfig and Makefile
Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Copy cpu/amd/pi/00670F00 to soc/amd/stoneyridge and
soc/amd/common. This is the second patch in the process of
converting Stoney Ridge to soc/.
Changes:
- update Kconfig and Makefiles
- update vendorcode/amd for new soc/ path
Change-Id: I8b6b1991372c2c6a02709777a73615a86e78ac26
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This
is the first of a series of patches to migrate Stoney Ridge
support from cpu, northbridge, and southbridge to soc/
Changes:
- add soc/amd/stoneyridge and soc/amd/common
- remove all other Husdon versions
- update include paths, etc
- clean up Kconfig and Makefile
- create chip.c to contain chip_ops
Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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