coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2018-05-23	mb/google/kahlee/dsdt.asl: Add method _SWS	Richard Spiegel
2018-05-18	soc/amd/stoneyridge: Support ACPI USB code generation	Duncan Laurie
2018-05-04	soc/amd/stonyridge: Add misc device	Akshu Agrawal
2018-02-06	soc/amd/stoneyridge/acpi/sleepstates.asl: Fix guarded code	Richard Spiegel
2018-02-05	soc/amd/stoneyridge/acpi/sb_pci0_fch.asl: Fix instability	Richard Spiegel
2018-01-13	soc/amd/stonyridge: Give I2C devices unique _UIDs	Daniel Kurtz
2017-11-28	AMD platforms: Fix ASL comment that implies "\_SB" is southbridge	Martin Roth
2017-11-22	Create SOC description file soc.asl	Richard Spiegel
2017-11-15	mb/{amd/gardenia,google/kahlee}: move carrizo_fch.asl code to soc	Richard Spiegel
2017-11-13	soc/amd/stoneyridge: Add CPU PPKG ASL	Marc Jones
2017-11-13	soc/amd/stoneyridge: Add GNVS variables for thermal control	Marc Jones
2017-10-20	soc/stoneyridge: Remove _PRW ASL	Marc Jones
2017-10-20	stoneyridge: Fix USB ASL	Marc Jones
2017-08-25	soc/amd/stoneyridge: Move IMC ASL source	Kyösti Mälkki
2017-08-23	soc/amd/stoneyridge ACPI: Sync sleepstates.asl definitions	Kyösti Mälkki
2017-08-14	stoneyridge: Fix CPU ASL \_PR table	Marc Jones
2017-08-14	stoneyridge: Rename hudson to southbridge	Marc Jones
2017-07-31	soc/amd/stoneyridge: Add GNVS	Marc Jones
2017-07-16	soc/amd/stoneyridge:Fix IS_ENABLED() around Kconfig symbol references	Martin Roth
2017-06-27	soc/amd/stoneyridge/acpi: Fix checkpatch errors	Marshall Dawson
2017-06-26	soc/amd/stoneyridge: Add northbridge support	Marc Jones
2017-06-26	soc/amd/stoneyridge: Add CPU files	Marc Jones
2017-06-26	soc: Add AMD Stoney Ridge southbridge code	Marc Jones