coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2018-06-13	amd/stoneyridge: Add early MTRR setup for new callouts	Marshall Dawson
2018-06-12	stoneyridge: Move agesa out of bootblock	Raul E Rangel
2018-05-22	bootblock: Allow more timestamps in bootblock_main_with_timestamp()	Julius Werner
2018-04-10	soc/amd/stoneyridege: Create AP jump structure	Richard Spiegel
2018-04-06	amd/stoneyridge: Use defined value for SPI flash MTRR	Marshall Dawson
2018-03-19	soc/amd/stoneyridge/southbridge.c: Remove configure_stoneyridge_uart	Richard Spiegel
2018-02-17	soc/amd/stoneyridge: Normalize GPIO init	Justin TerAvest
2018-01-30	soc/amd/stoneyridge: initialize i2c buses marked as early init	Aaron Durbin
2018-01-25	soc/amd/stoneyridge: remove dependence on TSC	Aaron Durbin
2018-01-23	soc/amd/stoneyridge: Add new function sb_program_gpio()	Richard Spiegel
2017-12-20	amd/stoneyridge: Force PSP command reg settings in bootblock	Marshall Dawson
2017-12-19	soc/amd/stoneyridge/bootblock/bootblock.c: Fix unused value	Richard Spiegel
2017-12-15	soc/amd/common: Update agesawrapper_call.h	Richard Spiegel
2017-12-12	soc/amd/common: Move Agesa related headers	Richard Spiegel
2017-11-14	soc/amd/stoneyridge: Load SMU fimware using PSP	Marshall Dawson
2017-11-08	amd/stoneyridge: Remove fixme.c	Marshall Dawson
2017-10-16	soc/amd/stoneyridge: Check UART index	Marshall Dawson
2017-08-14	stoneyridge: Rename hudson to southbridge	Marc Jones
2017-07-27	soc/amd/common: Convert to C_ENVIRONMENT_BOOTBLOCK	Marshall Dawson
2017-06-27	soc/amd/stoneyridge: Fix most checkpatch errors	Marshall Dawson
2017-06-26	soc: Add AMD Stoney Ridge southbridge code	Marc Jones