summaryrefslogtreecommitdiff
path: root/src/soc/amd/stoneyridge/include
AgeCommit message (Collapse)Author
2020-05-14soc/amd/stoneyridge: add resources during read_resources()Furquan Shaikh
The chipset code was incorrectly adding memory resources to the domain device after resource allocation occurred. It's not possible to get the correct view of the address space, and it's generally incorrect to not add resources during read_resources(). This change fixes the order by adding resources during read_resources(). Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I532f508936d5ec154cbcb3538949316ae4851105 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41369 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-28device: Constify struct device * parameter to acpi_inject_dsdtFurquan Shaikh
.acpi_inject_dsdt() does not need to modify the device structure. Hence, this change makes the struct device * parameter to acpi_inject_dsdt as const. Change-Id: I3b096d9a5a9d649193e32ea686d5de9f78124997 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40711 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28device: Constify struct device * parameter to write_acpi_tablesFurquan Shaikh
.write_acpi_tables() should not be updating the device structure. This change makes the struct device * argument to it as const. Change-Id: I50d013e83a404e0a0e3837ca16fa75c7eaa0e14a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-20soc/amd: replace remaining license headers with SPDX onesFelix Held
Change-Id: Ib45e93faebc2d24389f8739911419dfec437bd59 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-05soc/amd: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I22fffa0eab006be2bad4d3dd776b22ad9830faef Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-02soc/amd/common/psp: Move early init to socFelix Held
The initialization code in common//psp is very specific to Family 15h. Move this to the stoneyridge directory. BUG=b:130660285 TEST: Verify PSP functionality on google/grunt Change-Id: Ice3d06d6437f59a529c26fc2359565c940d39482 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/2020365 Reviewed-by: Eric Peers <epeers@google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-18soc: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-01-31soc/amd/stoneyridge: move to using smbus_host.h definitionsAaron Durbin
The SMBus function declarations were duplicated. Use the common ones provided by smbus_host.h. Change-Id: Ic912b91daf79ecd2c276a383edcda563891cf643 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38222 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-31soc/amd/stoneyridge: use SMBus timeout in compilation unitAaron Durbin
The timeout is fixed and only used in one place. Put the assumption in the compliation unit utilizing the defintion. Change-Id: I7537549da90d0bc158e638c533e8e8b0f1e28a7d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38612 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-31soc/amd/stoneyridge: use SMBus speed in compilation unitAaron Durbin
The fixed bus speed of 400 kHz doesn't need to reside in a header file. Just move the assumption into the code itself. Change-Id: I426fe078909a9b725c1747380d69af31292b6d1e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38611 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-04amdblocks/acpimmio: add common functions for AP entryMichał Żygowski
Move the stoneyridge implementation of get/set AP entry to the common block. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I9c73940ffe5f735dcd844911361355c384f617b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-12-04amdblocks/acpimmio: Unify BIOSRAM usageMichał Żygowski
All AMD CPU families supported in coreboot have BIOSRAM space. Looking at the source code, every family could have the same API to save and restore cbmem top or UMA base and size. Unify BIOSRAM layout and add implementation for cbmem top and UMA storing. Also replace the existing implementation of cbmem top and UMA with the BIOSRAM access. TEST=boot PC Engines apu1 and apu2 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I69a03e4f01d7fb2ffc9f8b5af73d7e4e7ec027da Reviewed-on: https://review.coreboot.org/c/coreboot/+/37402 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-28soc/amd/common: Remove guards on ACPIMMIO utilsKyösti Mälkki
If one wishes to use the functions guarded here, he has to have datasheet open anyways. It should be clear from there which regions are supported and which are not. TEST=Reproducible build of google/aleena. Change-Id: I0c1f0c9c9a6711532c5078c08cdf9e6612f3bc9c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-11-08arch/x86: Drop some __SMM__ guardsKyösti Mälkki
Change-Id: I64063bbae5b44f1f24566609a7f770c6d5f69fac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-21soc/amd/stoneyridge: Use new common SPI codeRichard Spiegel
Use the new SPI code from common folder, delete spi.c. SPI related macros must be single defined, in southbridge.h if they are used by files other than the common SPI code, fch_spi.h if they are only used by the common SPI code. The only exception is SPI_FIFO_DEPTH which must be in southbridge.h, because it can change between SOC. BUG=b:136595978 TEST=Build and boot grunt using new SPI code, with debug enabled. Check output. Change-Id: I639973d993316a10daa7564462e689b2c183f536 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-08-21arch/x86: Rename some mainboard_romstage_entry()Kyösti Mälkki
These platforms use different signature for this function, so declare them with different name to make room in global namespace. Change-Id: I77be9099bf20e00ae6770e9ffe12301eda028819 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34909 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-07cpu/x86/smm: Promote smm_subregion()Kyösti Mälkki
No need to limit these declarations to FSP. Both PARALLEL_MP_INIT smm_relocate() and TSEG_STAGE_CACHE can be built on top of this. Change-Id: I7b0b9b8c8bee03aabe251c50c47dc42f6596e169 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-07-31soc/amd/stoneyridge: Change code to accommodate Merlin Falcon SOCRichard Spiegel
Stoney Ridge is family 15h models 70h-7Fh, Merlin Falcon is family 15h models 60h-6Fh. Add changes based on config parameter SOC_AMD_MERLINFALCON to make the code backward compatible with Merlin Falcon. BUG=none. TEST=Tested later with padmelon board. Change-Id: I00fe832324500bcb07fca292a0a55f7258a2d82f Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33624 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-21soc/amd: Move SPI base alignment define into commonMarshall Dawson
The decision to leave the alignment in stoneyridge was driven because of a spec difference with picasso. AMD has checked the design materials and has confirmed there was no change. TEST=Build Grunt successfully BUG=b:130343127 Change-Id: If3a1d5a41dc175c9733fd09ad28627962646daf9 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-11soc/amd/common: Add errors for invalid AcpiMmio accessMarshall Dawson
Add a method for the soc/amd/<product> to indicate what AcpiMmio ranges are supported. Induce a build error if soc or mainboard code is added which attempts to use an unsupported block. This patch attempts to dissuade accessing unsupported blocks without requiring the complexity of structures or reinitializing at the beginning of a new stage. TEST=boot grunt, force build errors by removing blocks in iomap.h BUG=b:131682806 Change-Id: I2121df108fd3caf07e5588bc3201bcdd8dcaaa00 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-06-06src/amd/stoneyridge: Move alink source to commonMarshall Dawson
Relocate the alink access functions out of stoneyridge where they were dead code. This source maintains the ability to access all register spaces, however more modern APUs define only ABCFG in the BKDGs. BUG=b:131682806 Change-Id: I5c558ccc64bd04a66399c678d43beb0a97e72f63 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32663 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Add ALink-AHB Bridge to iomap.hMarshall Dawson
Add the address and replace the hardcoded value in the ASL code. Change-Id: If0b99de78d8c5948e2e5f2aa50dfc2efc1bd1ba1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32662 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Split sata functionalityMarshall Dawson
Separate chipset-specific source from sata_init(), and modify it to better match coreboot conventions. A subsequent patch will move the generic portion to soc/amd/common. The support for enabling port multipliers appears to have been first added for Kabini. Although missing from the documentation, the ability to affect the HBA Capabilities Register seems to remain for Stoney Ridge. Change-Id: I5dd9f613d36badc3e4d185a22b4475cb82ce187e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32660 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Remove sb_util.cMarshall Dawson
Obsolete pm_acpi_pm_cnt_blk(), and remove it and pm_acpi_pm_evt_blk(). Relocate the remaining functions to get/save UMA information to southbridge.c. Change-Id: I90c4394e3cf26f4ad60a078948a84303bda693d0 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32659 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Relocate MMIO access of ACPI registersMarshall Dawson
The AcpiMmio block allowing direct access to the ACPI registers has remained consistent across AMD models. Move the support from soc//stoneyridge to soc//common. BUG=b:131682806 Change-Id: I0e017a71f8efb4b614986cb327de398644599853 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32655 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Move LPC support to commonMarshall Dawson
AMD devices traditionally have the LPC-ISA bus at 14.3 and the definition has been very consistent. Relocate the feature from stoneyridge into common/block. BUG=b:131682806 Change-Id: I8d7175b8642bb17533bb2287b3e3ee3d52e85a75 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32653 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Rework SPI base address get/setMarshall Dawson
A subsequent patch will move the soc//stoneyridge LPC functionality to a common directory. Prepare by reworking the SPI BAR configuration function in southbridge.h. The SPI BAR is not a typical PCI BAR, and is at D14F3xA0. Change-Id: I73ddb4afaf9e67ca0522ecb6085b23c92fedc461 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32652 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Move GPIO support to commonMarshall Dawson
The banked GPIO functionality in the AcpiMmio block has been consistent since the Mullins product. Move the basic support into a common directory. Each product's pin availability, MUXes, and other details must remain specific to the product. The relocated source also drops the weak configure_gevent_smi() that reports SMI is not available. The stoneyridge port relies on SMI to do its initialization, similar to modern soc/intel devices. This is the plan for future soc/amd ports, so make a missing function a build error instead of a runtime warning. BUG=b:131682806 Change-Id: I9cda00210a74de2bd1308ad43e2b867d24a67845 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-03soc/amd/stoneyridge: Fix alignment in iomap.hMarshall Dawson
Change-Id: I79e8bc425d5db45abaeb655f86773f3bb1b2f8c4 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-29src/soc: Add missing 'include <types.h>'Elyes HAOUAS
<types.h> is supposed to provide <stdint.h> and <stddef.h>. When <types.h> is included, <stdint.h> and/or <stddef.h> is removed. Change-Id: I2db0a647bc657a3626cb5e78f23e9198e290261a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-05-16soc/amd/stoneyridge: Move I2C bus clear out of gpio.cMarshall Dawson
Relocate the I2C bus reset code from gpio.c to i2c.c. When it first went in, gpio.c was a natural location due to the nature of the algorithm. This is preparation for moving most of gpio.c to common code. Change-Id: I3b2d8e1b54e7c5929220d763bd99fe01b0636aaa Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32650 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-16soc/amd/common: Create AcpiMmio functionality from stoneyridgeMarshall Dawson
Move the stoneyridge AcpiMmio code into soc/amd/common. The SB800 southbridge introduced the MMIO hardware blocks at 0xfed80000 commonly known as AcpiMmio. Implementations beginning with Mullins enable decode in PMx04. Older designs use PMx24 and allow for configuring the base address. Future work may support the older version. Comparing the documentation for AMD's RRGs and BKDGs, it is evident that the block locations have not been reassigned across products. In some cases, address locations are deprecated and new ones consumed, e.g. the early GPIO blocks were simpler at offset 0x100 and the newer GPIO banks are now at 0x1500, 0x1600, and 0x1700. Note: Do not infer the definitions within the hardware blocks are consistent across family/model products. BUG=b:131682806 Change-Id: I083b6339cd29e72289e63c9331a815c46d71600d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32649 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-10soc/amd/stoneyridge: Add IO access functions for PMxMarshall Dawson
Replace locations in the source that explicitely use the CD6/CD7 index/data pair with utility function calls. Change-Id: I6e7ba472ef2551e363987d18a79408fcd2074de4 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-05-08soc/amd/stoneyridge: Add iomux read/write functionsMarshall Dawson
Add functions to read and write the region in the AcpiMmio block. Convert gpio.c to use them instead of creating pointers. Change-Id: I2a0f44b6ec7261648cf0357b44a6c18dd40d1504 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-05-08soc/amd/stoneyridge: Finish read/write misc registersMarshall Dawson
Add 16 and 32-bit versions of read / write_misc functions. Find one access of the MISC block still using read8() and write8(), and convert it. Change-Id: I296c521ea7f43210db406013bbe79362545ce6f3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-05-08soc/amd/stoneyridge: Add aoac_ read/write functionsMarshall Dawson
Add 8-bit functions to access the AOAC registers and use them in southbridge.c. At this time, there is no reason to pursue WORD or DWORD access and it's not known if those transaction sizes are supported. Change-Id: I3a8f493625f941fb855c0b8a0eff511a9a5ddfe8 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Martin Roth <martinroth@google.com>
2019-05-08soc/amd/stoneyridge: Rewrite smbus_read/write, add asfMarshall Dawson
Convert smbus_read8() and smbus_write8() functions to use the same arguments as the other AcpiMmio blocks, and add 16 and 32 bit versions. Add matching functions for the ASF controller. Change-Id: I3b0ecf21f20472245da98ab5e711a54e99dca93a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Martin Roth <martinroth@google.com>
2019-05-08soc/amd/stoneyridge: Rename AcpiMmio blocksMarshall Dawson
A subsequent patch will move the AcpiMmio support into amd/common. Take this opportunity to rename the blocks in the 0xfed8xxxx region with more consistency. Change-Id: I9a69a6ecfc10f78b4860df05a77a061d2fc8be7d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-04arch/io.h: Drop unnecessary includeKyösti Mälkki
Change-Id: I91158452680586ac676ea11c8589062880a31f91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31692 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-26soc/amd: Remove defined but unwritten functionsRichard Spiegel
There are functions defined on headers with no code written for. They probably existed earlier, were removed and forgot in the headers. Remove functions from headers if there's no actual code written for. BUG=b:123564495 TEST=Build grunt. Change-Id: Ia6a12e22a0944351c455dc2c3b534f09a258bd7b Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/31507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-02-15soc/amd/stoneyridge: Expand 48MHz for both osc out signalsRichard Spiegel
There are typically two configurable oscillator outputs available on APUs or FCHs. Convert the enable function to work with either one. BUG=b:none. TEST=Build and boot grunt. Change-Id: I4b89b1e3b7963472471e34897bdd00176dbdb914 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/31386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-02-01soc/amd/stoneyridge: Add generic PM1 register clear functionMarshall Dawson
Convert vboot_platform_prepare_reboot() to call a function in soc//stoneyridge. A subsequent patch will add another call to the new function, and this change removes any inference of a dependency on vboot. BUG=b:122725586 Change-Id: I634fcd030e206c790bda697a3dbef4e8cc21b3a8 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/31159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-01-30soc/amd/stoneyridge: Access SMBUS through MMIORichard Spiegel
Currently SMBUS registers are accessed through IO, but with stoneyridge they can be accessed through MMIO. This reduces the time of execution by a tiny amount (MMIO write is faster than IO write, though MMIO read is about as fast as IO read) as most of the time consumed is actually transaction time. Convert code to MMIO access. BUG=b:117754784 TEST=Used IO to write and MMIO to read, to confirm a one to one relationship between IO and MMIO. Then build and boot grunt. Change-Id: Ibe1471d1d578611e7d666f70bc97de4c3b74d7f8 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/29258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-01-28amd/stoneyridge: Disable GPIO MASK STATUSRaul E Rangel
MASK_STATUS disables interrupt status generation for the entire GPIO controller when any debounce register is configured. This causes problems when the kernel is loading drivers because we could lose interrupts for previously loaded devices. sb_program_gpios is also not setup to wait when configuring PAD_DEBOUNCE, so there is a potential that we could lose the interrupt status enable bit for other registers. By disabling MASK_STATUS we avoid that problem. BUG=b:113880780 BRANCH=none TEST=Ran a reboot stress test that concluded that we are no longer losing TPM interrupts while booting. Change-Id: Ife1db3b1449f205092509595cbc3eca511bff57a Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/31082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2019-01-23soc/amd/stoneyridge/gpio: Allow specifying 0 value for debounce timeoutDaniel Kurtz
It is possible to configure debounce, but leave it disabled by specifying a 0 value for the timeout. Add a define for allowing to do so via the PAD_DEBOUNCE() macro. Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> BUG=b:113880780 BRANCH=none TEST=compile Change-Id: I9de61297b0677cc904535a51c16970eecb52021d Reviewed-on: https://review.coreboot.org/c/30998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2019-01-21Revert "soc/amd/stoneyridge/gpio: Configure debounce for irq gpios"Raul Rangel
This reverts commit b82afce18aff24b6e5e3b73a67a6533cc4865a26. Reason for revert: This causes depthcharge to not boot due to TPM timeout errors. Because there is no wait after setting the debounce register, we lose data because the read-modify-write loses the interrupt status bit. e.g., GPIO 5 sets debounce, without a wait. Then GPIO 9 has it's debounce set. Because the interrupt controller is masking the interrupt enable status bit, the read-modify-write for GPIO9 loses the interrupt enable status bit and it never gets set again. This causes the interrupt to never latch. We should possibly make depthcharge set the interrupt enable status bit for latched GPIOs. Change-Id: Idd7259b14b24c441529d64e173be9faec03f4fc8 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/30981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2019-01-16soc/amd/stoneyridge/gpio: Configure debounce for irq gpiosDaniel Kurtz
FT4 has a strange property where whenever the debounce registers for any one gpio are changed, the FT4 disables interrupt propagation for ALL gpio irqs for ~4ms. In other words, if an edge interrupt of one gpio happens exactly during this debounce-irq-off window immediately following the configuration of another gpio, the interrupt will be lost. It is quite difficult to deal with this in the kernel, since during kernel boot time, drivers & devices are probed asynchronously, meaning it may happen that an already loaded driver may miss an interrupt when some later driver is being probed and configuring its gpio interrupt. To eliminate this possibility, we pre-configure the debounce registers in ram stage for all gpios that will be used as irqs later by the kernel using the same configuration as used by the kernel, as per this table: IRQ Debounce Edge Remove Glitch Level High Preserve Low Glitch Level Low Preserve High Glitch Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> BUG=b:113880780 BRANCH=none TEST=Reboot stress test grunt (>100 times); no messages in dmesg like: tpm tpm0: Timeout waiting for TPM ready Change-Id: I94c7ecfb14e5bb209b3598e10287c80eb19da25b Reviewed-on: https://review.coreboot.org/c/30921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-05 00:54:35 +0000