coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2019-05-16	soc/amd/common: Create AcpiMmio functionality from stoneyridge	Marshall Dawson
2019-04-23	src: Add missing include 'console.h'	Elyes HAOUAS
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
2019-03-04	arch/io.h: Drop unnecessary include	Kyösti Mälkki
2018-10-25	soc/amd/stoneyridge: Remove "else" after a return	Richard Spiegel
2018-10-18	cpu/amd: Use common AMD's MSR	Elyes HAOUAS
2018-09-11	amd/stoneyridge: Set BERT region size when no TSEG used	Marshall Dawson
2018-09-07	amd/stoneyridge: Adjust memory map for reserved	Marshall Dawson
2018-02-07	amd/stoneyridge: Put stage cache into TSEG	Marshall Dawson
2018-01-28	amd/stoneyridge: Add NV storage to ramtop	Marshall Dawson
2017-09-27	amd/stoneyridge: Enable SMM in TSEG	Marshall Dawson
2017-09-13	amd/stoneyridge: Make cbmem_top SMM aware	Marshall Dawson
2017-06-28	soc/amd/stoneyridge: Enable early cbmem	Marshall Dawson
2017-06-26	soc/amd/stoneyridge: Add northbridge support	Marc Jones