coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2019-03-04	arch/io.h: Add missing includes	Kyösti Mälkki
2018-12-19	amd/stoneyridge: Clear SMI_EVENT_STATUS when entering S3/S5	Edward Hill
2018-12-05	elog: make elog's SMM handler code follow everything else	Patrick Georgi
2018-12-03	soc/amd/stoneyridge: Use new ACPI MMIO functions	Richard Spiegel
2018-10-12	amd/stoneyridge: Fix PmControl register size in SMI handler	Marshall Dawson
2018-08-22	soc/amd/stoneyridge/smihandler.c: Report pending wake event	Richard Spiegel
2018-04-26	soc/amd/stoneyridge: Fix smi_write32 arg order in disable_all_smi_status	Daniel Kurtz
2018-04-26	soc/amd/stoneyridge: Static constify smi_sources	Daniel Kurtz
2018-02-10	soc/amd/stoneyridge: Put outl arguments in correct order	Martin Roth
2017-11-21	soc/amd/stoneyridge: Add ELOG to SMM	John E. Kabat Jr
2017-11-17	amd/stoneyridge: Add SlpTyp SMI handler	Marshall Dawson
2017-10-02	amd/stoneyridge: Refactor SMI handler	Marshall Dawson
2017-10-02	amd/stoneyridge: Clean up smihandler.c	Marshall Dawson
2017-10-02	amd/stoneyridge: Check SMI command address before reading	Marshall Dawson
2017-09-30	amd/stoneyridge: Use generic SMM command port values	Marshall Dawson
2017-09-27	amd/stoneyridge: Enable SMM in TSEG	Marshall Dawson
2017-08-14	stoneyridge: Rename hudson to southbridge	Marc Jones
2017-06-27	soc/amd/stoneyridge: Fix most checkpatch errors	Marshall Dawson
2017-06-26	soc: Add AMD Stoney Ridge southbridge code	Marc Jones