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2018-10-12amd/stoneyridge: Convert hex definitions to lower caseMarshall Dawson
Match the rest of the soc/stoneyridge source. Change-Id: I4531e6dad0362be73499647d9fc93c168b6f163e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-12amd/stoneyridge: Remove hudson register definitionsMarshall Dawson
Delete artifacts remaining from the original "hudson" and "yangtze" controller hub designs. Husdon devices had a configurable AcpiMmio base address, and a selection for I/O vs. MMIO decode. Modern products are fixed at 0xfed80000 in MMIO. Remove the flash control register definitions for the old generations. The manual reset register appears to not function as hudson. PMIO_DEBUG is named differently now, and not used, so remove its definition too. Change-Id: I6484bb2ca80b65318565dfee1a3368b121aea9de Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-11amd/stoneyridge: Indicate STAPM units in their nameRichard Spiegel
STAPM devicetree registers do not indicate the unit, which causes confusion. More importantly, the time was assumed to be in seconds when it's actually milliseconds. This caused early STAPM configurations to fail. BUG=b:117590953 TEST=Build grunt Change-Id: I2a7e3d43601992d1f7b02456913c763d940fe9ee Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29035 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-10soc/amd/stoneyridge/gpio.c: Create I2C slave reset codeRichard Spiegel
AMD's SOC do not wait for I2C transactions to complete before executing a reset. Because of this, it's possible for the reset to happen in the middle of a transaction, resulting on a slave hang. There are 2 possible solutions: If the slave has a reset pin connected to a GPIO pin, it can be used to reset the slave, else the only solution is to bang SCL 9 times. Create code that makes it easy to implement SCL bang, using a devicetree register to define which I2C SCL lines needs to be reset. BUG=b:114479395 TEST=Build and boot grunt. Look at transactions on a scope. Change-Id: I7f74b7e45c509044825355874753969f074e2382 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28574 Reviewed-by: Daniel Kurtz <djkurtz@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-05amd/stoneyridge: Comment PCI and AcpiMmio registers in ASLMarshall Dawson
TEST=Build Grunt BUG=b:77602074 Change-Id: I24a46cc3e766ba7e9199723b042476064a698bf2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-05amd/stoneyridge: Remove unused registers from ASLMarshall Dawson
Remove AcpiMmio and PCI config registers that are not used. TEST=build Grunt BUG=b:77602074 Change-Id: I62f40e421eba41c4a49d85efc975096171cb72fa Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-05amd/stoneyridge: Remove SATA D0 on suspendMarshall Dawson
Remove the step of setting the SATA controller to S0 as the system is entering S3. This had been duplicated from AMD's FchCarrizo.asl file, but upon closer inspection, the conditions for this step to run cannot be met. This does not affect Grunt's behavior, as the SATA controller is disabled. TEST=Suspend and resume Grunt BUG=b:77602074 Change-Id: Ib269a5363d03c7048abd0c8a9a28df92a773790c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-04amd/stoneyridge: Use BIOS_DEBUG to log PM1 and PMxC0 statusEdward Hill
Use BIOS_DEBUG consistently to log PM1 and PMxC0 status registers on boot. print_num_status_bits() was already using BIOS_DEBUG. TEST=Inspect console for Grunt BUG=b:110788201 Change-Id: If7da8c7c86e90a661338903ad05cc41e11f507d2 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://review.coreboot.org/28885 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-04amd/stoneyridge: Prepare for vboot rebooting systemMarshall Dawson
Implement the function vboot_platform_prepare_reboot() which is normally a weak function. The SlpTyp field of the PM1 register is not reset to its default value when the APU restarts. This change prevents a failing condition if vboot decides to reset the system instead of allowing an S3 resume to continue. TEST=Resume Grunt when vboot attempts a reset, verify a fresh boot instead BUG=b:117089826 Change-Id: I6e0e3e541bad89ca5b23d6ddb6e5c0df7f762f10 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28877 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-03soc/amd/stoneyridge: Add IOMMU supportMarc Jones
Enable the IOMMU in AGESA and copy the AGESA generated IVRS ACPI table. BUG=b:116196614 TEST=Check dmesg for AMD-Vi messages. Change-Id: I688d867c7bd4949a57b27c1b6a793c6a6e4a717a Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/28753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-01amd/stoneyridge: Add USB ASL for D0/D3coldMarshall Dawson
Add methods, and call them, for transitioning EHCI and xHCI to D0 or D3cold. Add device objects necessary for waking the system via USB. In order for USB to wake the system, it must be in the D3cold state. Then on resume, its firmware must be reloaded. This code relies heavily on AMD's FchCarrizo.asl (delivered in NDA PI package), and has been modified to fit the coreboot ASL names. In addition, AMD's methodology is to generate a SW SMI for saving/restoring certain settings. This has been ported into U3D0 and U3D3, as the necessary registers are now publicly documented. BUG=b:77602074 Change-Id: I83d0dce13411601691318cc67c99adf291ccf3bb Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28772 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-01amd/stoneyridge: Add ASL helper for AOAC PwrGood ControlMarshall Dawson
Add a method to assist with setting the PwrGood Control register, which will be useful for various devices. BUG=b:77602074 Change-Id: Ief602c4bc42d27b3e236d24db815b990f3a2419c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-01amd/stoneyridge: Add FCH WAK and PTS methodsMarshall Dawson
Add methods that can be used for preparing all controller hub devices for sleep, and that will turn the devices back on. BUG=b:77602074 Change-Id: I4b0c48e96aff23b4c31c9e89582b9fa80dba7bda Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28770 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-01amd/stoneyridge: Add ASL for D-states on AOAC devicesMarshall Dawson
Duplicate ASL from AMD's FchCarrizo.asl (available in NDA PI package) that can put AOAC devices into D0 or D3cold. The argument numbers coincide with the AOAC register offsets for the various devices. SATA, USB, and SD require additional device configuration. Add a placeholder and mark as todo. BUG=b:77602074 Change-Id: I32426f744a5ebbad9e8d3f2f37c4d214ad6dd3d4 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28769 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-01amd/stoneyridge: Add ACPI MMIO and PCI offsets to ASLMarshall Dawson
Define various AMD_SB_ACPI_MMIO_ADDR registers at 0xfed80000. Define various PCI config space registers. These are duplicated from AMD's FchCarrizo.asl file. BUG=b:77602074 Change-Id: Ie7447fef682424b05fa912b60c7b80112c6202de Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28768 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-01amd/stoneyridge: Load AOAC and USB gnvs valuesMarshall Dawson
Indicate the devices that are enabled. This is somewhat rudimentary, but could be improved in a later patch (e.g. get settings from devicetree). Calculate values that may be used for reinitializing the xHCI firmware. Add the EHCI BAR's current base address to gnvs. BUG=b:77602074 Change-Id: I8af69c030eb2353ad75beeb2bfd3bef24abff04c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28767 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-01amd/stoneyridge: Add USB settings to gnvsMarshall Dawson
A later patch will rely on two USB settings from the BIOS. Add these to the global_gnvs_t structure. The first is a data that will be used to locate the xHCI firmware for reloading after a resume. Although the existing calculations will be somewhat simple, keeping this on the coreboot side will help in the event multiple FWs are eventually in the build. The second item is a usable EHCI base address that may be programmed during S3 suspend and resume. At the time the PTS and WAK code runs, the BAR will be clear. BUG=b:77602074 Change-Id: I32205ac8a6908cca4a38dd68a7c7b591e76c06bb Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-01amd/stoneyridge: Create gnvs entries for AOAC devicesMarshall Dawson
A later patch will leverage AMD's ASL support for handling AOAC devices. This will gather coreboot's device enables from a bitwise field, where each bit corresponds to the register offset used to control each devices. Create an identical structure, and add it to the nvs ASL and global_nvs_t structure. BUG=b:77602074 Change-Id: I40f0161cc0bbc574ad703e34278372f2504de100 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-09-28amd/stoneyridge: Make gnvs ASL whitespace consistentMarshall Dawson
The globalnvs.asl file had become mixed with tabs and spaces to align columns. Use all tabs to align the comments. BUG=b:BUG=b:77602074 Change-Id: Ife4cf86372a8e24e78b38cca0254dd9fa00dd6b0 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-28soc/amd/stoneyridge/BiosCallOuts: Remove #include <AmdLib.h>Richard Spiegel
In preparation to remove AmdLib, remove reference to AmdLib.h in soc/amd/stoneyridge/BiosCallOuts. BUG=b:112525011 TEST=Buildgrunt. Change-Id: If80eb64fb736ff26ab226a16b583c8b1c29831f4 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28741 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Charles Marslett <charles.marslett@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-28src/*: normalize Google copyright headersPatrick Georgi
As per internal discussion, there's no "ChromiumOS Authors" that's meaningful outside the Chromium OS project, so change everything to the contemporary "Google LLC." While at it, also ensure consistency in the LLC variants (exactly one trailing period). "Google Inc" does not need to be touched, so leave them alone. Change-Id: Ia0780e31cdab879d2aaef62a2f0403e3db0a4ac8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/28756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com>
2018-09-24soc/amd/stoneyridge/romstage.c: Move STAPM code to SOC specificRichard Spiegel
STAPM programming was created inside function OemCustomizeInitEarly(). It should be SOC specific, and called by agesawrapper just before the call to OemCustomizeInitEarly(). BUG=b:116196626 TEST=build and boot grunt Change-Id: I8a2e51abda11a9d60a9057b38f2a484e1c8c9047 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28705 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-20soc/amd/stoneyridge/romstage.c: Remove obsolete commentRichard Spiegel
When preparing transition of AGESA calls to romstage, I placed a comment indicating the place to move a particular call. Now that the AGESA call has been moved to romstage, the comment became obsolete. BUG=b:116095766 TEST=none. Change-Id: I2811657385ab088747e32d4c66b99fdd01e7315e Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-09-19amd/stoneyridge: Sync PSP base to MSRMarshall Dawson
According to AMD, there exists an undocumented MSR which must be written with the PSP's base address. Read the value from the PSP's config space and sync each core's copy of the MSR to match. BUG=b:76167350 TEST=boot Grunt and verify "rdrand: disabled" goes away from dmesg Change-Id: I30027d3b0a6fbd540375e96001beb9c25bf3a678 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28608 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-17mb/google/kahlee/variants/baseboard: Set STAPM percentageRichard Spiegel
Default STAPM percentage causes a lot of thermal throttling on grunt. AMD experimented with 80%, it works for grunt. This is initial code to provide easy change path for other grunt based platforms. BUG=b:111608748 TEST=build and boot grunt. Change-Id: I22863f6ed76152bf872fce3e275f8a7fd8077504 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-12soc/amd/stoneyridge: Fix more GPIO functionsJonathan Neuschäfer
Instead of gpio_num, gpio_address should be used as the address in write32. This lets us also get rid of a few casts. Commit c9ed3ee8d8 ("soc/amd/stoneyridge: Fix gpio_set function") fixed one instance of this bug, but it was more widespread. TEST=None Change-Id: I0cf87aac2f1b87b6eac2b506515e48fe908c1f2b Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-11amd/stoneyridge: Enable BERT table generationMarshall Dawson
Add a duplicate ACPI_BERT symbol with a 'y' default setting and additional help text. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: I817111cbd3e81b93d8b02d0654ba68c8678b1bbe Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-09-11amd/stoneyridge: Set BERT region size when no TSEG usedMarshall Dawson
Expand the BERT reserved region size setting to account for the possibility of no TSEG configuration. This change is only for completeness, as stoneyridge must always use TSEG. Change-Id: I90753fa408cfac4de38aff08979c45349bb62a66 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-09-07amd/stoneyridge: Construct ACPI BERT tableMarshall Dawson
Add a Boot Error Record Table to the ACPI information. Avoid a driver error message by skipping the table altogether when no errors are found, or support isn't built in. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: I6fe38eefacaad0bc73d0cb4ae44a339a45857128 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28478 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07amd/stoneyridge: Construct BERT region from machine checkMarshall Dawson
Add functions to build a Boot Error Record Table region based on settings found in the MCA registers. Two entries are reported for each error due to the nature of the ACPI driver. The first is a Generic Processor Error, which the OS recognizes and parses. Generic errors cannot convey much error description or processor context. Therefore an IA32/X64 Processor Error is also added, which allows reporting the values found in the MCA MSR registers. Follow-on work could decode the MC errors more precisely, and better completing the Generic Error and the Check structure. The current level of support is sufficient to identify a (i.e., human readable) problem in dmesg, and provides adequate context information for analysis. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: I4d4ce29ddefa22aa29e6d3184f1adeaea1d5f837 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28477 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07amd/stoneyridge: Create an MCA structureMarshall Dawson
Convert the Machine Check reporting to use a newly defined structure. This will facilitate later patches that will pass pointers to the MSR values. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: I0a98aecc83a0fa1c5ca7926849a89145a595d9ff Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28476 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07amd/stoneyridge: Relocate MCA error identificationMarshall Dawson
Move the process of interrogating the Machine Check registers into its own file. This rearranges source code in preparation of supporting a Boot Error Record Table, which stoneyridge will use to report latent MC errors to the OS. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: Ia3275e9135dc96ba4a717c9371f38843fa1e3e64 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-07amd/stoneyridge: Adjust memory map for reservedMarshall Dawson
Carve out memory to be reported to the OS as reserved. This makes room for a region usable for Boot Error Record Table information. The BERT region reserved size is larger than likely requried, however the SMM region's base must be on a boundary matching the granularity of its size. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: I0958f6b6bab3fe9dae36c83e1fd9ae6ed0290a18 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28474 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-06chromeos/gnvs: remove function and naming cleanupJoel Kitching
- Remove unused acpi_get_chromeos_acpi_info (see CB:28190) - Make function naming in gnvs.h consistent (start with "chromeos_") BUG=b:112288216 TEST=compile and run on eve Change-Id: I5b0066bc311b0ea995fa30bca1cd9235dc9b7d1b Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/28406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-30soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port()Richard Spiegel
Function pci_ehci_dbg_set_port() used NDA register DEBUGPORT_MISC_CONTROL, which was deprecated in favor of a public PCI register (though only the bits to enable debug port became public) 0x90. Therefore code needs to be updated. BUG=b:69231009 TEST=Build and boot grunt. Change-Id: Ibb25992729d984b8570712f91a03a7cd1e9b8643 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-27update all FADT version 3.0 to use the get tables functionMarc Jones
Most FADT report using ACPIv3 FADT table. Using the get revision function keeps the table versions in sync. Change-Id: Ie554faf1be65c7034dd0836f0029cdc79eae1aed Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/28277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-22soc/amd/stoneyridge/smihandler.c: Report pending wake eventRichard Spiegel
There's a small window of opportunity when CPU is already in SMM but has not yet entered S3 for a wake event to happen, which would cause a failed S3 entry. Check for pending events at the very last moment possible, and if there are pending wake events report them. BUG=b:111100312 TEST=build and boot grunt. Change-Id: I9472fdf481897fcf9f4c669f6b1514ef479fce7a Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-22cbtable: remove chromeos_acpi from cbtableJoel Kitching
Since we can derive chromeos_acpi's location from that of ACPI GNVS, remove chromeos_acpi entry from cbtable and instead use acpi_gnvs + GVNS_CHROMEOS_ACPI_OFFSET. BUG=b:112288216 TEST=None CQ-DEPEND=CL:1179725 Change-Id: I74d8a9965a0ed7874ff03884e7a921fd725eace9 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/28190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-22acpi: remove CBMEM_ID_ACPI_GNVS_PTR entryJoel Kitching
Since we can retrieve the address of ACPI GNVS directly from CBMEM_ID_ACPI_GNVS, there is no need to store and update a pointer separately. TEST=Compile and run on Eve Signed-off-by: Joel Kitching <kitching@google.com> Change-Id: I59f3d0547a4a724e66617c791ad82c9f504cadea Reviewed-on: https://review.coreboot.org/28189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-17Fix PCI ACPI _OSC methodsMarc Jones
Fix the IASL build warnings: Object is not referenced (Name [CDW2] is within a method [_OSC]) Object is not referenced (Name [CDW3] is within a method [_OSC]) Remove the not referenced objects. They are not needed. BUG=b:112476331 TEST=IASL doesn't give the warning. Change-Id: I5b38d4de3f9875c5b013a49eb5146bf5916b96a6 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/28121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-16amd/stoneyridge: Add PMxC0 reset status to boot logEdward Hill
Print the PMxC0 S5/Reset status bits to the console. TEST=Inspect console for Grunt BUG=b:110788201 Change-Id: Ia905bb325a535fd4aa7082011cdfe92f08dff2cb Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://review.coreboot.org/28020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-08-15Stoneyridge: Remove VENDORCODE_FULL_SUPPORTRichard Spiegel
Remove VENDORCODE_FULL_SUPPORT from /soc/amd/stoneyridge/Kconfig and from vendorcode/amd/pi/00670F00/Makefile.inc, thus completing the removal of VENDORCODE_FULL_SUPPORT from coreboot. BUG=b:112578491 TEST=none, VENDORCODE_FULL_SUPPORT already not used. Change-Id: Idb5f6dc7add1617f7a97a97ae110901b2dec0996 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-14soc/amd/stoneyridge: Add bootblock_fch_initRaul E Rangel
Add a method in bootblock that can be used for printing registers. BUG=none TEST=compiled grunt Change-Id: I8dff30e589761fbad92cfc2709546dba169993d8 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28059 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-08soc/amd/stoneyridge: Prevent reboot in romstageRaul E Rangel
By setting this register in bootblock AmdInitEnv will no longer trigger a reset in romstage. This fixes a few vboot test failures and also speeds up boot time. BUG=b:111610455 TEST=Built grunt and made sure bootblock only happens once on cold boot, and S3 resume. Change-Id: Ie19f7a14deaef45ac63156bec6946273c1b9447e Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-08amd/stoneyridge: Dump MCA registersMarshall Dawson
Add a function to provide a rudimentary dump of the Machine Check Architecture registers. These values survive a warm reset. BUG=b:65445599 TEST=Verify on a Grunt having propensity for #MC errors Change-Id: Ib6875cabe3041e65c811d8b2232f7ac6bedd1a02 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-08amd/stoneyridge: Add warm reset detectionMarshall Dawson
Extend the existing reset handling features in Stoney Ridge to plan for, and recognize, warm resets. The ColdRstDet bit is always zero on a cold reset, and is intended as a mechanism for the BIOS to determine the type of a reset that occurred. Set ColdRstDet=1 after all cores have been initialized, so that any subsequent reset may be identified as warm/cold. A later patch will check the value during mp_init. Change-Id: I90255918de03018c9f090bff1e56a8bda5e7365e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-08cpu/amd: Correct number of MCA banks clearedMarshall Dawson
Use the value discovered in the MCG_CAP[Count] for the number of MCA status registers to clear. The generations should have the following number of banks: * Family 10h: 6 banks * Family 12h: 6 * Family 14h: 6 * Family 15h: 7 * Family 16h: 6 Change-Id: I0fc6d127a200b10fd484e051d84353cc61b27a41 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-08cpu/amd: Rename MCA status registerMarshall Dawson
Change the defined name of MCI_STATUS (i.e. MCi_STATUS) to reflect its MC0_STATUS address. Change-Id: I97d2631a186965bb8b18f544ed9648b3a71f5fb0 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-08soc/amd/stoneyridge/acpi.c: Remove fixed value variablesRichard Spiegel
In procedure generate_cpu_entries(), the code was copied from code that could change variables "plen" and "pcontrol_blk" based on number of cores. This is not the case with stoneyridge (2 cores only), and there's no need to use the variables. Remove them and replace with fixed values. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I0258b19960b050e8da9d218ded3f1f3bfccad163 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27877 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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