coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2021-02-12	soc/amd: select ACPI_AMD_HARDWARE_SLEEP_VALUES in common ACPI code	Felix Held
2021-02-12	soc/amd/*/Kconfig: remove redundant SMM_TSEG condition	Felix Held
2021-02-11	mainboards: Drop PWRS from GNVS	Kyösti Mälkki
2021-02-11	soc/amd/*/smihandler: use size_t and unsigned int	Felix Held
2021-02-11	soc/amd/*/smihandler: remove replace southbridge references with fch	Felix Held
2021-02-11	soc/amd: fully commonize clear_tvalid	Felix Held
2021-02-11	soc/amd: include cpu/x86/smm directory in common SMM Makefile	Felix Held
2021-02-11	soc/amd: move southbridge_smi_handler to common code	Felix Held
2021-02-11	soc/amd: factor out common SMM relocation code	Felix Held
2021-02-11	soc/amd*/smihandler: factor out and rename clear_smi_sci_status	Felix Held
2021-02-11	soc/amd*/smihandler: factor out and rename clear_all_smi_status	Felix Held
2021-02-11	soc/amd/stoneyridge: drop empty sb_enable	Felix Held
2021-02-10	soc/amd/stoneyridge/chip: rewrite enable_dev as switch case statement	Felix Held
2021-02-10	soc/amd/common/blocks/lpc: Remove common SPI registers	Raul E Rangel
2021-02-10	soc/amd/stoneyridge: Add SPI registers	Raul E Rangel
2021-02-10	soc/amd: Move southbridge_smi_set_eos to common/blocks/smi/smi_util	Felix Held
2021-02-10	soc/amd: Move global_smi_enable to common/blocks/smi/smi_util	Felix Held
2021-02-10	soc/amd: Move soc_route_sci to common/blocks/smi/smi_util	Felix Held
2021-02-09	soc/amd/stoneyridge/cpu: use MSR_PSP_ADDR define instead of hex number	Felix Held
2021-02-09	soc/amd/stoneyridge/memmap: drop __SIMPLE_DEVICE__	Felix Held
2021-02-09	soc/amd/stoneyridge/acpi: Convert to ASL 2.0	Elyes HAOUAS
2021-02-07	soc/amd/stoneyridge: remove STONEYRIDGE_ACPI_IO_BASE Kconfig option	Felix Held
2021-02-07	soc/amd/stoneyridge: remove STONEYRIDGE_ prefix of ACPI_IO_BASE define	Felix Held
2021-02-06	soc/amd/stoneyridge: Create chipset_power_state in romstage	Kyösti Mälkki
2021-02-03	soc/amd: rename sb_init_acpi_ports to fch_init_acpi_ports	Felix Held
2021-02-01	soc/amd: Drop PCNT from GNVS	Kyösti Mälkki
2021-02-01	soc/amd/stoneyridge/acpi: Convert to ASL 2.0 syntax	Elyes HAOUAS
2021-01-31	soc/amd/stoneyridge/psp: fix check of MSR_PSP_ADDR contents	Felix Held
2021-01-31	soc/amd/*/psp: move MSR_CU_CBBCFG to common and rename to MSR_PSP_ADDR	Felix Held
2021-01-31	soc/amd/stoneyridge/southbridge: move PSP BAR hide bit to its register	Felix Held
2021-01-30	soc/amd/stoneyridge/southbridge: replace southbridge prefix with fch	Felix Held
2021-01-29	device/Kconfig: Declare MMCONF symbols' type once	Angel Pons
2021-01-28	ACPI: Separate ChromeOS NVS in ASL	Kyösti Mälkki
2021-01-28	ACPI: Declare GNVS variables globally	Kyösti Mälkki
2021-01-27	soc/amd/stoneyridge: Change set_sb_nvs_final()	Kyösti Mälkki
2021-01-27	sb,soc/amd: Rename PMOD to PICM in ASL	Kyösti Mälkki
2021-01-26	soc/amd: Refactor some ACPI S3 calls	Kyösti Mälkki
2021-01-25	soc/amd: Refactor ACPI power state and ELOG	Kyösti Mälkki
2021-01-23	soc/amd: Rename chipset_state to chipset_power_state	Kyösti Mälkki
2021-01-19	soc/amd/picasso,stoneyridge: Unify set_nvs_sws()	Kyösti Mälkki
2021-01-19	soc/amd/stoneyridge: Add struct chipset_state	Kyösti Mälkki
2021-01-18	ACPI: Refactor ChromeOS specific ACPI GNVS	Kyösti Mälkki
2021-01-18	soc/amd/stoneyridge/romstage.c: Remove repeated word	Elyes HAOUAS
2021-01-15	build system: Always add coreboot.pre dependency to intermediates	Patrick Georgi
2021-01-15	build system: Remove flock calls from intermediate processing	Patrick Georgi
2021-01-14	build system: Structure and serialize INTERMEDIATE	Patrick Georgi
2021-01-14	soc/amd/stoneyridge: use SOC_AMD_COMMON_BLOCK_UART	Felix Held
2021-01-13	ACPI: Have single call-site for acpi_inject_nvsa()	Kyösti Mälkki
2021-01-13	ACPI: Add common acpi_fill_gnvs()	Kyösti Mälkki
2021-01-13	soc/amd: Rename to soc_fill_gnvs()	Kyösti Mälkki