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2020-12-22soc/amd/stoneyridge: Remove unused psp.hMarshall Dawson
psp.h was first included when Stoney Ridge began loading the first SMU firmware. That step was later moved from bootblock to romstage. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Id646390ce377143d09455f797de1b149dbb615b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48797 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-15soc/amd/common: Refactor SMBus base argumentsKyösti Mälkki
Replace SMBus base addresses with proper symbols. Change-Id: I5e0ebd7609c5c83d0e443ffba74dae68017d3ebc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42074 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-13soc/amd/*/include/spc/gpio: fix pin numbers in commentsFelix Held
Change-Id: I9e91f28659c49927aaa4c7cd67f73bb11258c27c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-12soc/amd/common: Refactor ACPIMMIO posted writesKyösti Mälkki
Change-Id: Ic1a5c17c789dd79fea8f348d1a9d32d4301ced88 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42825 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10soc/amd/stoneyridge/reset: use port and bit defines from cf9_reset.hFelix Held
The register name and the name of one bit are slightly different, but have the same functionality. Change-Id: Ie49975bb43868cbb2dc986e66dc5b7291e70222f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48507 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09soc/amd/picasso,stoneyridge: drop unused BIOSRAM offset definesFelix Held
The two Socs don't use this functionality and biosram.c in the common code is the only place where those defines are used, but it doesn't include soc/iomap.h and has its own definitions instead. Change-Id: I973df4ab39a94e89ea2ed6ffb639c5a85b8df456 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09soc/amd: factor out functionality to print last reset sourceFelix Held
Change-Id: I5cec38dac7ea27aa316f5dd4f91ed84627a0f937 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09soc/amd: factor out legacy I/O and cf9 decode enable functionsFelix Held
Replace sb prefix with fch prefix, since those are all FCHs and no south bridges any more. Verstage on PSP uses the I/O access mechanism instead of the MMIO one, so keep a separate function for that, but also move it to the common mmio_util file to have them all in one place. Change-Id: I47dac9ee3d9e27f7b7a5fddab17cf4fc10de6c3e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48435 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09soc/amd: factor out PM_DECODE_EN register definitionsFelix Held
Change-Id: I005709a8780725339e7c08fbfff94e89c8ef26da Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09soc/amd: remove unused PM_ISA_CONTROL definitionsFelix Held
ACPIMMIO_DECODE_REGISTER_04 is the definition in the common ACPIMMIO code block that actually gets used. Also fix the indentation of the ACPIMMIO register decode defines in the common code. Change-Id: Ib2c460541be768fe05d8cc3d19a14dbd9c114a45 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09soc/amd/stoneyridge/southbridge: make sb_disable_4dw_burst staticFelix Held
sb_disable_4dw_burst is only used in the same compilation unit, so no need to make it externally visible. Change-Id: I6c7c96f67b98fb8ed808f45a7685c4d72a10d32c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-06soc/amd/stoneyridge: remove unused config_t typedefFelix Held
Change-Id: I1456fe069c4b0cf859f769e0144ec62cff0f3987 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-06soc/amd/stoneyridge/chip.h: remove unneeded extern pci_domain_opsFelix Held
Now pci_domain_ops in chip.c can also be marked as static. Change-Id: I5e481fe311c9db4aacfd94bbf671edf679528946 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-06soc/amd/stoneyridge/acpi/sb_fch: use existing base address definesFelix Held
TEST=Identical timeless build for amd/gardenia. Change-Id: I04952cdbbe7893f35a674a156a9bc22202fbdc2f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48311 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-05soc/amd/stoneyridge: order selected Kconfig options alphabeticallyFelix Held
TEST=Timeless build doesn't change for amd/gardenia. Change-Id: I5f1873111c07f6dc823b06654e463830d83acc9e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-05amd_blobs: Always set default pathsNico Huber
Don't make the default paths to AMD blobs depend on USE_AMD_BLOBS. This way we get error messages about the missing files when the blobs repos aren't checked out. Change-Id: I754fdc5e1414c8a3dc88b364bcfbea9a26b59eb0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-04soc/amd: move smi_util to common blockFelix Held
The functionality in smi_util applies for all 3 AMD SoCs in tree. This patch additionally drops the HAVE_SMI_HANDLER guards in the common block's Makefile.inc, since all 3 SoCs unconditionally select HAVE_SMI_HANDLER in their Kconfig and smi_util doesn't use any functionality that is only present when that option is selected. Change-Id: I2f930287840bf7aa958f19786c7f1146c683c93e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-03src: Remove redundant use of ACPI offset(0)Elyes HAOUAS
IASL version 20180927 and greater, detects Unnecessary/redundant uses of the Offset() operator within a Field Unit list. It then sends a remark "^ Unnecessary/redundant use of Offset" example: OperationRegion (OPR1, SystemMemory, 0x100, 0x100) Field (OPR1) { Offset (0), // Never needed FLD1, 32, Offset (4), // Redundant, offset is already 4 (bytes) FLD2, 8, Offset (64), // OK use of Offset. FLD3, 16, } We will have those remarks: dsdt.asl 14: Offset (0), Remark 2158 - ^ Unnecessary/redundant use of Offset operator dsdt.asl 16: Offset (4), Remark 2158 - ^ Unnecessary/redundant use of Offset operator Change-Id: I260a79ef77025b4befbccc21f5999f89d90c1154 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43283 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02soc/amd: factor out common SMI/SCI enums and function prototypesFelix Held
At least a part or the remaining definitions in the soc-specific smi.h files are also common, but those have to be verified more closely. Change-Id: I5a3858e793331a8d2ec262371fa22abac044fd4a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-02soc/amd: factor out fch_smbus_initFelix Held
Change-Id: I6df9323dc4e7ca99fd5368f0262e850c0aca5c54 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-02soc/amd: factor out SMBUS controller registers into common headerFelix Held
The patch also rewrites the bit definition using shifts to make them easier to read. The older non-SoC chips can probably also use the new header file, but for this patch the scope is limited to soc/amd, since the older non-SoC chips don't use the SMBUS controller code in soc/amd/common. TEST=Timeless build for amd/mandolin and amd/gardenia doesn't change. Change-Id: Ifd5e7e64a41f1cb20cdc4d6ad1e675d7f2de352b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-02soc/amd: factor out common AOAC device enable and status query functionsFelix Held
The code on Stoneyridge didn't set the FCH_AOAC_TARGET_DEVICE_STATE bits to FCH_AOAC_D0_INITIALIZED like the code for Picasso does, but that is the default value after reset for those bits on both platforms. Change-Id: I7cae23257ae54da73b713fe88aca5edfa4656754 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-02soc/amd: factor out common AOAC definitionsFelix Held
The register locations and bit definitions are the same for Stoneyridge and Picasso. Since not all devices are present on all SoCs, keep those numbers in the SoC-specific code. Change-Id: Ib882927e399031c376738e5a35793b3d7654b9cf Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-01soc/amd/stoneyridge: align AOAC code with PicassoFelix Held
In commit 09d50671e6b43c23853a91ff4d6fb26c1e7e17a1 the AOAC code was reworked for Picasso and this patch ports this back to Stoneyridge to facilitate factoring out the functionality into common code. Change-Id: I836b91dc647987d064170fff7c8ca6ef2ee49211 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-30soc/amd: move bootblock inside main SoC directoriesFelix Held
There's no need to have the bootblock in its own sub-directory, so move it to each SoC's main directory to avoid clutter. This makes soc/amd more consistent with the coreboot code base in src/northbridge, src/southbridge and src/soc with the exception of src/soc/intel. Change-Id: I78a9ce1cd0d790250a66c82bb1d8aa6c3b4f7162 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47982 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-21soc/amd: factor out vbnv_cmos_failed() into soc/amd/common/vbootFelix Held
Change-Id: I7f976c6c5a2a715e1a5372bb93fe657d0d86c848 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47584 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-18soc/amd/common: remove SOC_AMD_COMMON_BLOCK Kconfig symbolFelix Held
SOC_AMD_COMMON needs to be selected to be able to select SOC_AMD_COMMON_BLOCK which only includes the Kconfig files from the function block sub-folder. Removing SOC_AMD_COMMON_BLOCK and the corresponding Kconfig file and make SOC_AMD_COMMON include all Kconfig files from the sub-folders simplifies this a bit. Change-Id: I9068d57a80bdc144e73d2b8c00e7b2cae730d4b6 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-16soc/amd/stoneyridge: unify and align include guards with picassoFelix Held
Change-Id: I0cc06e33ed5c9b9bd97ed1f10f9c2d8019b1b5ac Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47582 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13soc/amd: factor out _SOC_DEV macro into common blockFelix Held
TEST=Timeless build doesn't change for Mandolin and Gardenia. Change-Id: I1aef68459569536207697bfca407145a7b5334f4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-09soc/amd/*/smi.h: Move the pm_acpi_smi_cmd_port function declarationArthur Heymans
This prototype will be used outside of soc/amd. Change-Id: Icc69cf8a910764b27edf64f0f527b8f6a9013121 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45813 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-06amdfwtool: Use shell command to get depend file listZheng Bao
The amdfwtool is not available at the beginning of the building. So it may have error if it is missing. Change-Id: Id4db70986755cef8e98877c4e92841b25ced5452 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-04soc/amd: Change FIRMWARE_LOCATE to FIRMWARE_LOCATIONZheng Bao
Change-Id: I3a3d187fc24ab752dfe61893c15561a92d009fe2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46062 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30{soc/amd,sb/amd/hudson}: Fix generating the ACPI mcfgArthur Heymans
The last argument for acpi_fill_mcfg() is the last PCI bus, which is an uint8_t, not the total number of busses, which overflows the argument if CONFIG_MMCONF_BUS_NUMBER is 256. Change-Id: I8887e14128dbe54688eb6e803d6694b7c29956c1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-10-30amdfwtool: Take a config file instead of command line parametersZheng Bao
To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-02drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES configShelley Chen
Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate older x86 platforms that don't allow writing to SPI flash when early stages are running XIP from flash. If BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is not selected, BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY will get auto-selected if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y. This allows for current platforms that write to flash in the earlier stages, assuming that they have that capability. BUG=b:150502246 BRANCH=None TEST=diff the coreboot.rom files resulting from running ./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a --timeless with and without this change to make sure that there was no difference. Also did this for GOOGLE_CANDY board, which is baytrail based (and has BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES enabled). Change-Id: I3aef8be702f55873233610b8e20d0662aa951ca7 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-26arch/x86: Introduce `ARCH_ALL_STAGES_X86_32`Angel Pons
Nearly every x86 platform uses the same arch for all stages. The only exception is Picasso. So, factor out redundant symbols from the rest. Alder Lake is not yet complete, so it has been skipped for now. Change-Id: I7cff9efbc44546807d9af089292c69fb0acc7bad Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-21soc/amd: Drop unneeded empty linesElyes HAOUAS
Change-Id: Ib262955a1d26681c796c4b10d2b336f2715824d0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-20soc/amd/picasso: Fix typo of Kconfig settingZheng Bao
USE_PSPSCUREOS -> USE_PSPSECUREOS. Change-Id: I5c89975cc317cb93e79509e885010d14a79dd7e1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-15soc/amd/stoneyridge/acpi/sb_pci0_fch: remove duplicate I/O rangeFelix Held
This I/O region is already covered by the range declared right above the deleted one. Change-Id: I8b8ff3385bbba8e69101ee2c5a5cb39c8f996b94 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45369 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-12include/console/uart: make index parameter unsignedFelix Held
The UART index is never negative, so make it unsigned and drop the checks for the index to be non-negative. Change-Id: I64bd60bd2a3b82552cb3ac6524792b9ac6c09a94 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-17soc/amd/stoneyridge: remove unused soc_power_reg objectAaron Durbin
Now that no one is consuming this object, remove its definition. BUG=b:159947207 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ib5aeec1733b6c9fa49569e30c4c369f70af0939c Reviewed-on: https://review.coreboot.org/c/coreboot/+/44487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-17soc/amd/stoneyridge: use new ACPI helper functions from commonAaron Durbin
Transition the current call sequence to using the newly added common ACPI helper functions. Semantically, the expectations are that this sequence is the equivalent of previous acpi_clear_pm1_status(). BUG=b:159947207 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Id3ae19013c68d2c97b084046f600596ecc462374 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-11soc/amd/stoneyridge/acpi: clean up global NVSFelix Held
Some fields in GNVS seem to be copied over from Apollolake to Stoneyridge. This patch removes the unused fields. Change-Id: I135c4a4547668fe67e74d0ea9ae3a03c3687375f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-28src/soc/amd: Add include <types.h>Elyes HAOUAS
BIT(x) needs <types.h>. Change-Id: Icaeda969cae52d9c62d976db4ead0e734efa838c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-27soc/amd: Use spi_writeX & spi_readX for all spi accessesMartin Roth
BUG=b:161366241 TEST=Build & boot Trembyle Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ied7789e9315c75174df9a686c831c5a969ce3bfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/43773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-07-26soc/amd/common: Refactor and consolidate code for spi baseMartin Roth
Previously, the spi base address code was using a number of different functions in a way that didn't work for use on the PSP. This patch consolidates all of that to a single saved value that gets the LPC SPI base address by default on X86, and allows the PSP to set it to a different value. BUG=b:159811539 TEST=Build with following patch to set the SPI speed in psp_verstage. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I50d9de269bcb88fbf510056a6216e22a050cae6b Reviewed-on: https://review.coreboot.org/c/coreboot/+/43307 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20src: Make HAVE_CF9_RESET set the FADT reset registerAngel Pons
All supported x86 chips select HAVE_CF9_RESET, and also use 0xcf9 as reset register in FADT. How unsurprising. We might as well use that information to automatically fill in the FADT accordingly. So, do it. To avoid having x86-specific code under arch-agnostic `acpi/`, create a new optional `arch_fill_fadt` function, and override it for x86 systems. Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of the patch train, both operating systems are able to boot successfully. Change-Id: Ib436b04aafd66c3ddfa205b870c1e95afb3e846d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-07-20src: Drop useless cache flush settings in FADTAngel Pons
They are ignored if the ACPI_FADT_WBINVD flag is set, which is required on current ACPI versions and only maintained for ACPI 1.0 compatibility. Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of the patch train, both operating systems are able to boot successfully. Change-Id: Ief1219542ba71d18153b64180e0ff60bd1e7687b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-07-20soc/amd/stoneyridge: Select HAVE_CF9_RESETAngel Pons
Looks like some preparation is needed before reset. However, Picasso also needs some special handling and still selects this option without selecting HAVE_CF9_RESET_PREPARE. So, just add HAVE_CF9_RESET for now. Change-Id: I0c6da9a43a28dbee916fd6bda9ae380ebd619edf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43388 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20src: Never overwrite `fadt->flags`Angel Pons
Instead, just flip the desired bits using bitwise operations. As this is initially zero, the resulting value is the same. This allows flags to be set from anywhere regardless of execution order. Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of the patch train, both operating systems are able to boot successfully. Change-Id: Icfd580a20524936cd0adac574331b09fb2aea925 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43387 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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