coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2021-02-11	soc/amd: fully commonize clear_tvalid	Felix Held
2021-02-11	soc/amd/cezanne/smihandler: add missing southbridge_io_trap_handler	Felix Held
2021-02-11	soc/amd: include cpu/x86/smm directory in common SMM Makefile	Felix Held
2021-02-11	soc/amd: move southbridge_smi_handler to common code	Felix Held
2021-02-11	soc/amd: factor out common SMM relocation code	Felix Held
2021-02-11	soc/amd*/smihandler: factor out and rename clear_smi_sci_status	Felix Held
2021-02-11	soc/amd*/smihandler: factor out and rename clear_all_smi_status	Felix Held
2021-02-11	soc/amd/cezanne: add empty SMM-handler	Felix Held
2021-02-11	soc/amd/stoneyridge: drop empty sb_enable	Felix Held
2021-02-10	soc/amd/cezanne/fch: add HAVE_SMI_HANDLER case to fch_init_acpi_ports	Felix Held
2021-02-10	soc/amd/stoneyridge/chip: rewrite enable_dev as switch case statement	Felix Held
2021-02-10	soc/amd/cezanne: Add verstage support	Raul E Rangel
2021-02-10	soc/amd/common/psp_gen2: print error for uninitialized MSR_PSP_ADDR	Felix Held
2021-02-10	soc/amd/common/block/psp: factor out soc_get_psp_base_address	Felix Held
2021-02-10	soc/amd/cezanne: Enable SOC_AMD_COMMON_BLOCK_SPI	Raul E Rangel
2021-02-10	soc/amd/common/blocks/lpc: Remove common SPI registers	Raul E Rangel
2021-02-10	soc/amd/cezanne: Add SPI registers	Raul E Rangel
2021-02-10	soc/amd/picasso: Add SPI registers	Raul E Rangel
2021-02-10	soc/amd/stoneyridge: Add SPI registers	Raul E Rangel
2021-02-10	soc/amd/common/block: Fix guards for PSP transfer buffer	Raul E Rangel
2021-02-10	soc/amd/common/block/cpu/noncar: Remove unneeded whitespace before tab	Elyes HAOUAS
2021-02-10	soc/amd/picasso/smihandler: replace southbridge.c in comment with fch.c	Felix Held
2021-02-10	soc/amd/cezanne/chip: add empty set_mmio_dev_ops	Felix Held
2021-02-10	soc/amd/cezanne/chip: add empty cpu_bus_ops	Felix Held
2021-02-10	soc/amd/block/psp/psp: raise log level of PSP failure messages	Felix Held
2021-02-10	soc/amd: Move southbridge_smi_set_eos to common/blocks/smi/smi_util	Felix Held
2021-02-10	soc/amd: Move global_smi_enable to common/blocks/smi/smi_util	Felix Held
2021-02-10	soc/amd: Move soc_route_sci to common/blocks/smi/smi_util	Felix Held
2021-02-10	soc/amd/picasso: Move APM_CNT_SMMINFO callsite	Kyösti Mälkki
2021-02-09	Revert "soc/amd/picasso: Change GPIO _HID to AMDI0030"	Martin Roth
2021-02-09	soc/amd/picasso/cpu: move set_cstate_io_addr to common code	Felix Held
2021-02-09	soc/amd/picasso/cpu: move get_cpu_count to common code	Felix Held
2021-02-09	soc/amd/cezanne: Add root_complex	Raul E Rangel
2021-02-09	soc/amd/stoneyridge/cpu: use MSR_PSP_ADDR define instead of hex number	Felix Held
2021-02-09	soc/amd/cezanne: add empty CPU driver	Felix Held
2021-02-09	soc/amd/cezanne: Enable early LPC support in bootblock stage	Zheng Bao
2021-02-09	soc/amd/picasso: move smm_region to soc/amd/common/block/cpu/noncar	Felix Held
2021-02-09	soc/amd/picasso/memmap: drop __SIMPLE_DEVICE__	Felix Held
2021-02-09	soc/amd/stoneyridge/memmap: drop __SIMPLE_DEVICE__	Felix Held
2021-02-09	src: Add missing <cbmem.h>	Elyes HAOUAS
2021-02-09	soc/amd,intel: Drop s3_resume parameter on FSP-S functions	Kyösti Mälkki
2021-02-09	soc/amd/stoneyridge/acpi: Convert to ASL 2.0	Elyes HAOUAS
2021-02-08	soc/amd/common/memmap: add comment about types in memmap_early_dram	Felix Held
2021-02-08	soc/amd/picasso/iomap: change ACPI_CPU_CONTROL to match AGESA	Felix Held
2021-02-07	src: Remove redundant include <rules.h>	Elyes HAOUAS
2021-02-07	soc/amd/stoneyridge: remove STONEYRIDGE_ACPI_IO_BASE Kconfig option	Felix Held
2021-02-07	soc/amd/stoneyridge: remove STONEYRIDGE_ prefix of ACPI_IO_BASE define	Felix Held
2021-02-07	soc/amd/cezanne/romstage: Store early dram region	Raul E Rangel
2021-02-07	soc/amd/picasso: Move memmap_early_dram to common blocks	Raul E Rangel
2021-02-07	soc/amd/cezanne/Makefile.inc: Fix indentation	Raul E Rangel