summaryrefslogtreecommitdiff
path: root/src/soc/amd
AgeCommit message (Collapse)Author
2021-02-11soc/amd: fully commonize clear_tvalidFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I90526a566a5fbc19a7368f90421067a6c716614e Reviewed-on: https://review.coreboot.org/c/coreboot/+/50466 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11soc/amd/cezanne/smihandler: add missing southbridge_io_trap_handlerFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4140fbf93e84a2620ffb88e5c65df17b23135553 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50465 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11soc/amd: include cpu/x86/smm directory in common SMM MakefileFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id6be7aa7f295e61f873bfae1fca42260d3b0db78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50464 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11soc/amd: move southbridge_smi_handler to common codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I650498321736eee3d33af51216eda1b650f11744 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50463 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11soc/amd: factor out common SMM relocation codeFelix Held
The common code gets moved to soc/amd/common/block/cpu/smm, since it is related to the CPU cores and soc/amd/common/block/smi is about the SMI/ SCI functionality in the FCH part. Also relocation_handler gets renamed to smm_relocation_handler to keep it clear what it does, since it got moved to another compilation unit. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I45224131dfd52247018c5ca19cb37c44062b03eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/50462 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11soc/amd*/smihandler: factor out and rename clear_smi_sci_statusFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifd6c3bebee1ccf7e7e7987d8ae3d9fa654019791 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50460 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11soc/amd*/smihandler: factor out and rename clear_all_smi_statusFelix Held
The old name was misleading, since it doesn't disable the generation of SMIs, but clears the status registers. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iddadbec013091c2e5993a6303e291451c3d1e7ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/50459 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11soc/amd/cezanne: add empty SMM-handlerFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I95908fac3b1e17a16542e5d80001fac3d22d839a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50455 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11soc/amd/stoneyridge: drop empty sb_enableFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9b6e0bd5c7358e2f18f929d5b098d95acbf59a5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/50437 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10soc/amd/cezanne/fch: add HAVE_SMI_HANDLER case to fch_init_acpi_portsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie7bab29ae8d0e28c392210f8dcbaa4441ca61114 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50454 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10soc/amd/stoneyridge/chip: rewrite enable_dev as switch case statementFelix Held
This also aligns Stoneyridge with Picasso and Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I35bf9915e3502c22e9dd9efa80b00a1ce70f187d Reviewed-on: https://review.coreboot.org/c/coreboot/+/50436 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10soc/amd/cezanne: Add verstage supportRaul E Rangel
Setup the config required to support verstage. The offsets are the same as picasso. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I82874d649db3c9c370e32841e6a9898efb70082e Reviewed-on: https://review.coreboot.org/c/coreboot/+/50342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-02-10soc/amd/common/psp_gen2: print error for uninitialized MSR_PSP_ADDRFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8b6362a9eb2344293dad22357651f646774af789 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50448 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10soc/amd/common/block/psp: factor out soc_get_psp_base_addressFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib73ac92e69f1be5852a1406ba714acb6a8a04989 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-10soc/amd/cezanne: Enable SOC_AMD_COMMON_BLOCK_SPIRaul E Rangel
Required so we pass SPI information down to depthcharge. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4ce819b537333c28d394c925331e3dbf260b7732 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10soc/amd/common/blocks/lpc: Remove common SPI registersRaul E Rangel
Use the SoC versions instead. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia0b8129b165f8a2e6be6706ab2e3f2d39e1025a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-10soc/amd/cezanne: Add SPI registersRaul E Rangel
These are identical to picasso. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3ef4c51ef6d656b3b035d97a56b1875b40e89210 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-10soc/amd/picasso: Add SPI registersRaul E Rangel
The picasso SPI registers are different than the ones defined in amdblocks/lpc.h. The BASE_ALIGNMENT has changed and the PSP_SPI_MMIO_SEL bit has been added. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0b5a0c88c6dbb95cdbc62b949a7d30bfad1fa725 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-10soc/amd/stoneyridge: Add SPI registersRaul E Rangel
This is a copy/paste of amdblocks/lpc.h. The registers are different for picasso and cezanne, so I'm moving them to soc. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4dfadcdc025d3581cb1423e9793a9b2181742b9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/50443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-10soc/amd/common/block: Fix guards for PSP transfer bufferRaul E Rangel
The transfer buffer is only required when using VBOOT_STARTS_BEFORE_BOOTBLOCK. The VBOOT workbuffer is only required when VBOOT_STARTS_BEFORE_BOOTBLOCK or VBOOT_STARTS_IN_BOOTBLOCK. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I444bede3f2b716e1900e7621453351d7fddadaa3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-10soc/amd/common/block/cpu/noncar: Remove unneeded whitespace before tabElyes HAOUAS
Change-Id: Ib88358ca26876cd25247cd9619fb2b70f6859ac2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10soc/amd/picasso/smihandler: replace southbridge.c in comment with fch.cFelix Held
southbridge.c was renamed and split into early_fch.c and fch.c. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie439e746fb3dfe9ec865481a76a09eab378242bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/50458 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10soc/amd/cezanne/chip: add empty set_mmio_dev_opsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2ac5fcd17b6aed464a0d1e55f2860574501f7a8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-10soc/amd/cezanne/chip: add empty cpu_bus_opsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I658294c84d64c7de0ccfa74b0e830d787a3a42fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/50438 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10soc/amd/block/psp/psp: raise log level of PSP failure messagesFelix Held
If the PSP didn't like a command this should be at least a warning on the console and not just a debug message. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If7e5f6320631cca86813e98f82b8c0c21bf18af1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10soc/amd: Move southbridge_smi_set_eos to common/blocks/smi/smi_utilFelix Held
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I69466143315c1c9870a97c9ef8f68ed85f38e779 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50415 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10soc/amd: Move global_smi_enable to common/blocks/smi/smi_utilFelix Held
Change-Id: I4410772a8d3f2dedbb96601d87efb23b14e5f438 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42989 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10soc/amd: Move soc_route_sci to common/blocks/smi/smi_utilFelix Held
Change-Id: Ic379723c0bf6e5edf5f3d63cc11b24d0e59b5075 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42988 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10soc/amd/picasso: Move APM_CNT_SMMINFO callsiteKyösti Mälkki
Triggering SMI is not part of the semantics of global_smi_enable(), so move it to the post_mp_init handler. Even without the !acpi_is_wakeup_s3 check we don't get PSP warnings/errors during resume, so we can drop the workaround introduced in commit 5dbe45e0f5608794e03634aed28530ddb2ab9ac5 in this patch. Change-Id: Id0e7723c2bb9811f80fe36c38199a01445dc1d7d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42987 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-09Revert "soc/amd/picasso: Change GPIO _HID to AMDI0030"Martin Roth
This reverts commit 75f6ab35ffefec72e343175686d7ef45b30b0939. Reason for revert: The 5.4 Linux kernel is not configured for AMDI0030. This causes an issue where the WP pin is not recognized. BUG=b:179320024 TEST=WP pin shows up properly in crossystem after reverting this change. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I0850fd085b5ee70522752633900f69d4d3732321 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50052 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-09soc/amd/picasso/cpu: move set_cstate_io_addr to common codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3b8a38ea39d8dc56ff1249a3212fe352b3e805ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/50407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-09soc/amd/picasso/cpu: move get_cpu_count to common codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0690787f492d764a20a4219822eb10fb5cd86de0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-09soc/amd/cezanne: Add root_complexRaul E Rangel
This is a copy/paste of picasso with a few things removed. With this change we can jump into depthcharge. Allocated resources: PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 2 PCI: 00:00.0 resource base 100000 size 1f00000 align 0 gran 0 limit 0 flags e0004200 index 3 PCI: 00:00.0 resource base 2000000 size 1c0000 align 0 gran 0 limit 0 flags f0004200 index 4 PCI: 00:00.0 resource base 21c0000 size cde40000 align 0 gran 0 limit 0 flags e0004200 index 5 PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:00.0 resource base 100000000 size 30e340000 align 0 gran 0 limit 0 flags e0004200 index 6 PCI: 00:00.0 resource base 40e340000 size cc0000 align 0 gran 0 limit 0 flags f0004200 index 7 PCI: 00:00.0 resource base 40f000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index 8 PCI: 00:00.0 resource base 410000000 size 20000000 align 0 gran 0 limit 0 flags f0004200 index 9 PCI: 00:00.0 resource base cfffe000 size 2000 align 0 gran 0 limit 0 flags f0004200 index a PCI: 00:00.0 resource base ceffe000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b TEST=Boot majolica and see depthcharge finally loading: Starting depthcharge on MAJOLICA... new_rt5682_codec: chip = 0x1A Looking for NVMe Controller 0x3004cac8 @ 00:01:07 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I52682ec2a06c7e219c221648f241e18e26a9358e Reviewed-on: https://review.coreboot.org/c/coreboot/+/50339 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-09soc/amd/stoneyridge/cpu: use MSR_PSP_ADDR define instead of hex numberFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id9042def0f5e9d2fa994d6729c592c7e2152976b Reviewed-on: https://review.coreboot.org/c/coreboot/+/50405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-09soc/amd/cezanne: add empty CPU driverFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I54299cadae4cb562e04a16c3b8e051c9c454db79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-09soc/amd/cezanne: Enable early LPC support in bootblock stageZheng Bao
Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I739d97ddc5afd84a4bbc7e505b423158eb820767 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-09soc/amd/picasso: move smm_region to soc/amd/common/block/cpu/noncarFelix Held
The same functionality is needed on Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I40f9d2fe7d144e94369a417225bcca0a299d1f45 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-09soc/amd/picasso/memmap: drop __SIMPLE_DEVICE__Felix Held
No PCI or PNP functions are used in here. TEST=Timeless build results in identical image. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I577e2ecdc59dbd09e739ae800cbe021168a34812 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50399 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-09soc/amd/stoneyridge/memmap: drop __SIMPLE_DEVICE__Felix Held
No PCI or PNP functions are used in here. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I46851656db1f1866a82f06ceab67c93019cc6af1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-02-09src: Add missing <cbmem.h>Elyes HAOUAS
Change-Id: I75a816c594b326df8a4aa5458bb055fca35e1741 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-09soc/amd,intel: Drop s3_resume parameter on FSP-S functionsKyösti Mälkki
ACPI S3 is a global state and it is no longer needed to pass it as a parameter. Change-Id: Id0639a47ea65c210b9a79e6ca89cee819e7769b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-09soc/amd/stoneyridge/acpi: Convert to ASL 2.0Elyes HAOUAS
Change-Id: I71c296cdc0180a2832aeb51434de3302a54b5db8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-08soc/amd/common/memmap: add comment about types in memmap_early_dramFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reported-by: Angel Pons <th3fanbus@gmail.com> Change-Id: I295bfcb05571492adbe81ffc579a835be4abffe1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-08soc/amd/picasso/iomap: change ACPI_CPU_CONTROL to match AGESAFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I80e11d9792ee4138cb376ebbe0438dc304b54527 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50288 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-07src: Remove redundant include <rules.h>Elyes HAOUAS
Change-Id: Ie4692246d059734bb5bad6c64042b64068636ab6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-07soc/amd/stoneyridge: remove STONEYRIDGE_ACPI_IO_BASE Kconfig optionFelix Held
No board in tree selects a different base address, so this can be removed from Kconfig and be treated like the other base addresses in the I/O space that are defines in iomap.h. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iec3d4476e3a6a5d2b226edef4c41f503a0c81f33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-07soc/amd/stoneyridge: remove STONEYRIDGE_ prefix of ACPI_IO_BASE defineFelix Held
Since I'm not sure if there are non-upstream boards that change the default of the Kconfig value and the comment says that it needs to match the binaryPI build, I'll do that change in a follow-up patch to allow easy local reverts of that. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic0f08c6cb951994be6db19e10f73f0c621521c70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-07soc/amd/cezanne/romstage: Store early dram regionRaul E Rangel
Needed so we can reserve the memory. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I8f5bb9d97932f75ca4ce22fbe9df4c0148acbea5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-07soc/amd/picasso: Move memmap_early_dram to common blocksRaul E Rangel
We need the same functionality for cezanne. TEST=Boot ezknil Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0800c662bb473eb571c74e76a8247298f534b53f Reviewed-on: https://review.coreboot.org/c/coreboot/+/50337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-07soc/amd/cezanne/Makefile.inc: Fix indentationRaul E Rangel
We don't use spaces. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Id617e98db5b0895071ee98265f68f6106058bd63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-10 14:57:27 +0000