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2019-08-16amd/picasso: Unify SMM relocationKyösti Mälkki
Change-Id: I62104894b5a956523f509d88d49e45a0bd1c587d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34749 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-16amd/stoneyridge: Unify SMM relocationKyösti Mälkki
Change-Id: I02ad07e049cb74ccb52ba3d41eb16c58a2cfb38b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34748 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-16amd/stoneyridge: Rename ramtop.c to memmap.cKyösti Mälkki
Use a name consistent with the more recent soc/intel. Change-Id: I4d67a7c3107758c81a67e1668875767beccfcdb0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-08-16amd/picasso: Rename ramtop.c to memmap.cKyösti Mälkki
Use a name consistent with the more recent soc/intel. Change-Id: I491e609bed00dc79c628b321c74ad7f4cc31b5fe Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-08-16soc/amd/common: Refactor S3 helpersKyösti Mälkki
Make the prototypes match what drivers/amd/agesa would rather see, in preparation to use the same code with open-source AGESA. Change-Id: I1506ee2f7ecf3cb6ec4cce37a030c05f78ec6d59 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-15soc/*: mp_run_on_all_cpus: Remove configurable timeoutPatrick Rudolph
Some timeouts given were too small when serial console is enabled due to its spinlock making code runtime worse with every AP present. In addition we usually don't know how long specific code runs and how long ago it was sent to the APs. Remove the timeout argument from mp_run_on_all_cpus and instead wait up to 1 second, to prevent possible crashing of secondary APs still processing the old job. Tested on Supermicro X11SSH-TF. Change-Id: I456be647b159f7a2ea7d94986a24424e56dcc8c4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-08-15cpu/x86/smm: Promote smm_memory_map()Kyösti Mälkki
Change-Id: I909e9b5fead317928d3513a677cfab25e3c42f64 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34792 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15cpu/x86/smm: Define single smm_subregion()Kyösti Mälkki
At the moment we only have two splitting of TSEG, one with and one without IED. They can all use same implementation. Make configuration problems of TSEG region assertion failures. Rename file from stage_cache.c to tseg_region.c to reflect it's purpose. Change-Id: I9daf0dec8fbaaa1f4e6004ea034869f43412d7d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34776 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Guckian Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-13cpu/x86: Move some SMM function declarationsKyösti Mälkki
Change-Id: I9a4e57f8fd032f2824eab0e5b59d635710e3e24b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-08-13cpu/x86: Separate save_state struct headersKyösti Mälkki
Any platform should need just one of these. Change-Id: Ia0ff8eff152cbd3d82e8b372ec662d3737078d35 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34820 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-11arch/x86: Flip option NO_CAR_GLOBAL_MIGRATIONKyösti Mälkki
It is easier to track CAR_GLOBAL_MIGRATION which is the approach to be deprecated with the next release. This change enforces new policy; POSTCAR_STAGE=y is not allowed together with CAR_GLOBAL_MIGRATION=y. Change-Id: I0dbad6a14e68bf566ac0f151dc8ea259e5ae2250 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-08-11arch/x86: Enable POSTCAR_CONSOLE by defaultKyösti Mälkki
Almost all platforms force it on. Make it enabled by default but under user control to optionally disable it. Change-Id: I6b0f19c8bfd6ffed93023d57a1d28ca6acc06835 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-09soc/amd/picasso: Update i2c supportMarshall Dawson
Change the stoneyridge definitions into picasso. The named 0 and 1 buses are controlled by the PSP and not directly accessible by host firmware. I2C4 operates only in slave mode so is not added to to the bus clear-after-reset sequence. The I2C controller is fundamentally the same as on Stoney Ridge so the ability to clear a potentially jammed bus is still required. Program Picasso's new pad control registers in the MISC AcpiMmio space according to the recommended settings. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ibbc5504ebc36654e28c79fe3ae17cc0d9255118f Reviewed-on: https://review.coreboot.org/c/coreboot/+/33763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-09soc/amd/picasso: Update CPU supportMarshall Dawson
Change the Stoney Ridge ID to Picasso. Rename family 15h. Get the number of cores/threads from CPUID as all D18 registers are new. Change-Id: I44c45db637897f6caf320032c9f79a3a1ab4d6c9 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-09soc/amd/picasso: Reduce 48M out configurationMarshall Dawson
Picasso has only a single 48M output. Simplify the setup function. Note that while the feature is similar to older products, the register definition and Enable bit has changed. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Iebaf5219fdcd3145a4faf906f656a7fbdc7e0c36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-09soc/amd/picasso: Remove IOAPIC2Marshall Dawson
Remove the Family 15h device. It's not in Family 17h documentation and isn't detectable with HDT. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ifa9c06f78f39a3ec3b555d4ecc542172cd44a0b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33990 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-09soc/amd/picasso: Update SMI sourcesMarshall Dawson
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I42bb0edb6fa2c6fa92829ef5d3623483aa448a5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/33771 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-09soc/amd/picasso: Update machine check supportMarshall Dawson
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Iae48a0c3fb2abf2aa3fb78af8d50431c8533f76f Reviewed-on: https://review.coreboot.org/c/coreboot/+/33769 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-09src/amd/picasso: Update reset codeMarshall Dawson
Remove the scratch register indicators. Per AMD, AGESA no longer uses these. Use a new IO register to determine whether a warm reset should occur. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I0ff7935004b3d1ac5204d3ef575cfa98116a57fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/33989 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-09soc/amd/common: Add new GPIO 8K pull-up definitionMarshall Dawson
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: If24bed8b3f10d945b9988445025409c8420dd07a Reviewed-on: https://review.coreboot.org/c/coreboot/+/33762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-09src/soc/amd/picasso: Update GPIO configurationMarshall Dawson
Make the definitions match Picasso's definitions. Add/remove pins that differ from stoneyridge, update GEVENTs for the FCH mapping. Change-Id: I59f958151f27ed4ca0eb1a87ade6102eec1e5061 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-09amd/stoneyridge,picasso: Open TSEG earlierKyösti Mälkki
Don't make assumptions about which subregion will be accessed first. Change-Id: I558fa4acc5068014b3748be6fc1bc34999054c0a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34775 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-08arch/x86: Handle smm_subregion() failureKyösti Mälkki
The callers don't necessarily check return value of function. Make sure the parameters are not left uninitialised in that case. Change-Id: Ic02db2d35b2ec88506320e7df609940de4aef005 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34708 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-08arch/x86: Change smm_subregion() prototypeKyösti Mälkki
Do this to avoid some amount of explicit typecasting that would be required otherwise. Change-Id: I5bc2c3c1dd579f7c6c3d3354c0691e4ba3c778e1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-08arch/x86: Move TSEG_STAGE_CACHE implementationKyösti Mälkki
This is declared weak so that platforms that do not have smm_subregion() can provide their own implementation. Change-Id: Ide815b45cbc21a295b8e58434644e82920e84e31 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-08lib/stage_cache: Refactor Kconfig optionsKyösti Mälkki
Add explicit CBMEM_STAGE_CACHE option. Rename CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM to TSEG_STAGE_CACHE. Platforms with SMM_TSEG=y always need to implement stage_cache_external_region(). It is allowed to return with a region of size 0 to effectively disable the cache. There are no provisions in Kconfig to degrade from TSEG_STAGE_CACHE to CBMEM_STAGE_CACHE. As a security measure CBMEM_STAGE_CACHE default is changed to disabled. AGESA platforms without TSEG will experience slower S3 resume speed unless they explicitly select the option. Change-Id: Ibbdc701ea85b5a3208ca4e98c428b05b6d4e5340 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-07soc/amd/picasso: Set HAVE_BOOTBLOCK=nKyösti Mälkki
Change-Id: Iaf370e04adb04eb81555a57e81812ebe3339971d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-08-07soc/amd: Rename smm_region_info() to smm_region()Kyösti Mälkki
Change-Id: I361fb0e02fd0bd92bb1e13fe84c898a1ac85aa40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34703 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-07cpu/x86/smm: Promote smm_subregion()Kyösti Mälkki
No need to limit these declarations to FSP. Both PARALLEL_MP_INIT smm_relocate() and TSEG_STAGE_CACHE can be built on top of this. Change-Id: I7b0b9b8c8bee03aabe251c50c47dc42f6596e169 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-06soc/*: Report mp_init errorsPatrick Rudolph
* Increase log level from ERR to CRITICAL in run_ap_work(). * Print or return errors if mp_run_on_all_cpus() failed. Tested on Supermicro X11SSH-TF. Change-Id: I740505e3b6a46ebb3311d0e6b9669e7f929f9ab9 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-31soc/amd/stoneyridge: Change code to accommodate Merlin Falcon SOCRichard Spiegel
Stoney Ridge is family 15h models 70h-7Fh, Merlin Falcon is family 15h models 60h-6Fh. Add changes based on config parameter SOC_AMD_MERLINFALCON to make the code backward compatible with Merlin Falcon. BUG=none. TEST=Tested later with padmelon board. Change-Id: I00fe832324500bcb07fca292a0a55f7258a2d82f Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33624 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-21soc/amd/picasso: Remove dead SPD size Kconfig symbolMarshall Dawson
DIMM_SPD_SIZE is no longer used and should have been removed in 78025f6 "soc/amd/picasso: Remove all AGESA references". Change-Id: Iae15998835e4d8afdb44cca77d2c9009b7e3947a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-21soc/amd/picasso: Enable stage cache only with ACPI resumeMarshall Dawson
Make the option match the change in I7c3b3ec. "stoneyridge/Kconfig: Enable stage cache based on HAVE_ACPI_RESUME" Change-Id: I7fa13428ec0119b61f429116a52986067e833bdf Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-21soc/amd: Move SPI base alignment define into commonMarshall Dawson
The decision to leave the alignment in stoneyridge was driven because of a spec difference with picasso. AMD has checked the design materials and has confirmed there was no change. TEST=Build Grunt successfully BUG=b:130343127 Change-Id: If3a1d5a41dc175c9733fd09ad28627962646daf9 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-17amd/stoneyridge/Kconfig: Enable stage cache based on HAVE_ACPI_RESUMESubrata Banik
This patch fixes inconsistent issue with stage cache enabling with HAVE_ACPI_RESUME config enable. Only enable stage cache if CONFIG_HAVE_ACPI_RESUME=y Change-Id: I7c3b3ec4642a615e17fb3dbdedca6af8ca95ea2b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-07-17soc/amd/stoneyridge: Add Merlin Falcon configurationRichard Spiegel
Add config parameter for Merlin Falcon (SOC_AMD_MERLINFALCON) and modify the Makefile.inc based on this config parameter. BUG=none. TEST=Tested later with padmelon board. Change-Id: Id9f960b8f012c5a1cfd398611d6a51838493da27 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-09arch/x86: Flip HAVE_MONOTONIC_TIMER defaultKyösti Mälkki
Change-Id: Id56139a3d0840684b13179821a77bc8ae28e05ae Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-09cpu/x86: Flip SMM_TSEG defaultKyösti Mälkki
This is only a qualifier between TSEG and ASEG. Change-Id: I8051df92d9014e3574f6e7d5b6f1d6677fe77c82 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-09soc/amd/stoneyridge,picasso: Switch SMM lock conditionKyösti Mälkki
SMM_TSEG is a qualifier between TSEG and ASEG memory region. ASEG is deprecated and not supported for this platform in coreboot codebase. The SMM lock should be set based on whether SMM is installed or not, HAVE_SMI_HANDLER currently tells that. Change-Id: I9756f8a59ccfedd59d5b997b35313452dd0c4f46 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34127 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-06soc/amd/picasso: Remove all AGESA referencesMarshall Dawson
Family 17h will not use the Arch2008 (a.k.a. v5) wrapper. Remove all source, support functions, and comments related to AGESA. Family 17h requires v9 which has no similarities to v5 for integration into a host firmware. AGESA v9 support will be added via subsequent patches into the appropriate locations. Change-Id: Iea1a41941a0ba364a6abaaf31cc8e1145db4a236 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-04arch/x86: Adjust size of postcar stackKyösti Mälkki
With VBOOT=y && VBOOT_MEASURED_BOOT=y message digest will be allocated from the stack and 1 KiB reserve used with the recent platforms was no longer sufficient. The comment of LZMA scratchpad consuming stack was obsolete for postcar, so these can be reduced to same 4 KiB. Change-Id: Iba1fb5bfad6946f316feac2d8c998a782142a56a Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-07-03soc/amd/common/lpc: Add Picasso IDMarshall Dawson
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I02e6fdcd6685e0dd3fa7872b054ebe508157a0ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/33758 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-03soc/amd/common/iommu: Add Picasso IDMarshall Dawson
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ib000e12cd568dd83b9533efe66e67878b806b3f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-07-03soc/amd/common/hda: Add Picasso IDsMarshall Dawson
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I02b279a2b625ecbdf827cb4643d772eb81ddfe70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-07-03soc/amd/picasso: Remove all PSP runtime functionsMarshall Dawson
Remove the mailbox call to notify the PSP that DRAM is ready. This is not supported on Family 17h. Remove the selectable SMU firmware. This is a feature of the PSP bootloader and the standard bootloader doesn't contain the ability. Clean up additional mentions of PSP within picasso. Change-Id: I8abeb4c375dbff3b438cd18ccaaf66e11c86e72e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-07-03soc/amd/picasso: Remove fanless SKU optionMarshall Dawson
The command line options for picasso will look different than stoneyridge. Remove the fanned/fanless distinction to simplify the makefile. Picasso will use subprograms instead of fanned/fanless SKUs. Change-Id: I50d8751e14b00ca53a6498f8e6c7f3f42543dace Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33753 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-03soc/amd/picasso: Remove SD controllerMarshall Dawson
Change-Id: Ie9cf361ed0caba9c73727453c4a503557edc854d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-03soc/amd/picasso: Add xhci1 and remove ehciMarshall Dawson
Change-Id: I9d0098082c224bbf5ab2b4f0f41eb8b5b729eec7 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-03soc/amd/picasso: Remove most stoneyridge USBMarshall Dawson
Picasso doesn't implement the AcpiMmio XHCI_PM registers. Remove source that uses these. Remove USB devices from the AOAC registers. Remove the D0/D3 support from ASL, including all supporting xHCI firmware loading support. Remove xHCI firmware from amdfw.rom. Change-Id: Iae4c72c5a8e353ca8db02d04735f8d2b28441793 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-07-03soc/amd/picasso: Remove stoneyridge GECMarshall Dawson
Remove the hudson-style support for the Gigabit Ethernet Controller. Change-Id: I2124b949a866148a97d9cd6e7fd418f7de8e2216 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 09:38:00 +0000