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2018-08-01soc/amd/stoneyridge/lpc.c: Fix LPC host control namingRichard Spiegel
2 bits of LPC host control were originally not public, and wrongly identified as IMC related. Now that the bits are available in public BKDG, fix the naming of the bits. BUG=b:111912080 TEST=build and boot grunt. Change-Id: I1921f46c6be54eda6329c98267cec27004caadd5 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27744 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-31src/soc/amd/stoneyridge: Remove IMC supportRichard Spiegel
Per AMD, the Integrated Micro Controller is not a supported feature of the Stoney Ridge APU. Systems are expected to implement an external EC for desired features. Remove all stoney IMC files and functions from src/soc/amd/stoneyridge. There are 2 "IMC bits" left (and used) that are not truly IMC. New BKDG describe these bits, so a new patch will be released later to fix the names and comment. BUG=b:111780177 TEST=Build grunt and gardenia Change-Id: I6a24e4c3f03d04713a030b884c611d9c64c4cb3a Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27651 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30soc/amd/stoneyridge/northbridge.c: Create a way to change eDP training valueRichard Spiegel
The careena board needs different video settings to pass eye diagram test, which does not affect negatively the grunt board. In preparation for new VBIOS, create code that allows changing eDP training parameter. BUG=b:111673328 TEST=Tested in child patch. Change-Id: Ic0452618bfc5e05b9ef8280bb8ba398ec7b4ce95 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-27soc/amd/stoneyridge: Add IGFX device ACPI ASL entryMarc Jones
Add internal graphics device 00.01.00 to the ACPI tables so that the ACPI PCI option ROM save functions have a proper scope to save the ROM to. BUG=b:111697181 TEST=Check coreboot log doesn't have "PCI: 00:01.0: Missing ACPI scope" and check _ROM method is added in the SSDT1. Change-Id: I2c9ef8d9dff76805b1fcde2ccceef958a5b53b4f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-07-18mainboard/google/Kahlee: Select low-power mode for WiFiSimon Glass
Put the PCIe clock pins in power-saving mode for the WiFi module to save power. Note: This currently does not appear to have any effect on grunt. BUG=b:110041917 BRANCH=none TEST=boot without this patch: $ iotools mem_read32 0xfed80e00 0x0046f3ff With this patch: $ iotools mem_read32 0xfed80e00 0x0046f3f1 Change-Id: I389815bc36b8610a30b0cbb9d73262ad392e0181 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/27465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-17soc/amd/stoneyridge: Update ACPI external processor nameKevin Chiu
update external processor name to match declaration in SSDT. in SSDT: Processor (\_PR.P000, 0x00, 0x00000410, 0x06) {} Processor (\_PR.P001, 0x01, 0x00000000, 0x00) {} in DSDT: External (_PR_.CP00, UnknownObj) External (_PR_.CP01, UnknownObj) After fix this, ACPI _PSL (Passive List) now can return correct list of processor objects for thermal passive cooling. BUG=b:111478152 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I78c838608c78eb7b5e3f8d5c67589e082c756201 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/27495 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-16soc/amd/stoneyridge: Add GPIO functions to SMMMarc Jones
GPIO functions are required by the Grunt SMI handler. Change-Id: Id729139b02c10bdd922b3df298f8f9feb1aff745 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-16soc/amd/stoneyridge: Fix gpio_set functionMarc Jones
The gpio_set function was not writing the correct GPIO register address. Change-Id: Ib306773ac72505977b606836bbaf3e2067324894 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-09src/soc: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: I21680354f33916b7b4d913f51a842b5d6c2ecef3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-03soc/amd/stoneyridge: correct GPIO emission error in ACPIKevin Chiu
It can not emit byte data without BytePrefix. design to: Or (Local5, GPIO_PIN_OUT, Local5) error due to GPIO_PIN_OUT is 0x40 but 0x40 encoding means nothing in AML spec. so it will include next emitted string in Or: Or (Local5, Local5, \_SB.GPW2) fix: Store (0x40, Local0) Or (Local5, Local0, Local5) BUG=b:110962003 BRANCH=master TEST=emerge-grunt coreboot extract SSDT then check ACPI syntax is correct Change-Id: I7a0704112b77105826de87b14a38ed2f665224d5 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/27306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-02stoneyridge: Enable legacy IORaul E Rangel
Legacy IO enables access to RTC IO 0x70-0x73. This is needed for CMOS to function correctly. BUG=b:110817463 TEST=ran firmware_CorruptFwSigB on grunt Change-Id: I533226ba764f567e348577d7fcf6ebe43336609a Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-02stoneyridge: Enable IO CF9 in bootblockRaul E Rangel
If IO CF9 is not enabled, hard_reset() won't do anything in bootblock or verstage. BUG=b:110817463 TEST=built on grunt and made sure that hard_reset() reboots. Change-Id: I5f091077a17db3dfe5b8e8367163312db6828360 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27267 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-02soc/amd/common: Change create_struct return valueKyösti Mälkki
Old return value was not used, and function body has die() in case of errors in allocation. Change-Id: I89b0e9c927d395ac6d27201e0b3a8658e9585187 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/27261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-02soc/amd/common: Fix agesawrapper CreateStruct callsKyösti Mälkki
When AllocationMethod == ByHost, buffer has to be provided by caller. Improve code symmetry, the named parameter is now always pointer to the struct. Change-Id: I2085f7d5d63ef96f4bd9d5194af099634c402820 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/27112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-06-28amd/common/pi: Remove AGESA support files from bootblockMarshall Dawson
The stoneyridge bootblock no longer makes AGESA calls. Remove the support files from the bootblock build. TEST=boot Grunt Change-Id: I14d2336d5fb766a1acf5e812337ae0ab3ca4a6c1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-28amd/common/pi: Remove obsolete heapmanager workaroundMarshall Dawson
Remove residual code that allowed successful building of the heapmanager code. Now that stoneyridge no longer makes AGESA calls in bootblock, it is safe to elimate the workaround. BUG=b:74518368 TEST=boot Grunt Change-Id: Ie169a691a177bcd8283c31c8188ce28bcbce82af Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-26soc/amd/stoneyridge/southbridge.c: Fix get_index_bit limit checkRichard Spiegel
Limit is the maximum number of bits to be tested, however it's being checked against the number of bytes of uint32_t. when it should be number of bits. Create a macro to provide the number of bits, and use it instead of sizeof. BUG=b:75996437 TEST=Add debug messages to see code passing beyond the check, build and boot grunt, check that it passed the limit check, remove debug code. Change-Id: Id1dfda26d789183b346b20c37fec923d996b80db Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-25mb/google/kahlee/variants/grunt: Select low-power mode for BayHub720Simon Glass
Put the PCIe clock pins in power-saving mode for the BayHub eMMC bridge to save power. This requires use of an additional register (Misc control register 2) and another bit in the existing 'protect' register. The naming of bit 0 of that register is incorrect, based on the latest datasheet (14 June 2018) so fix that too. BUG=b:73726008 BRANCH=none TEST=boot without this patch: iotools mem_read32 0xfed80e00 0x0046ffff With this patch: $ iotools mem_read32 0xfed80e00 0x00463fff Also see that the PCIe clock stops when eMMC is idle and can be started by starting disk activity. Change-Id: I5ad1467b2e2e151215d2dfd2ce48cd4a451fe480 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/26515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-21soc/amd/stoneyridge/southbridge.c: Store PM related registers in cbmemRichard Spiegel
PM registers used for generating SWS values are being stored in a static variable within southbridge.c. In order to have it available for any source involved in building the platform, move the storage to cbmem, using id CBMEM_ID_POWER_STATE. Also add a variable that informs from which state the system is waking from, extracted from register ACPI_PM1_CNT_BLK. This variable will later be useful in detecting failed S3 resume. BUG=b:80119811 TEST=Add code to print SWS parameters and state it's waking from. Build and boot grunt, suspend and resume, check output for valid values. Remove the print code. Change-Id: Ib27a743b7e7f8c94918caf7ba5efd473f4054986 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27109 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21soc/amd/common: Always set GetBiosCalloutKyösti Mälkki
The entire StdHeader field is really supposed to be forked from a template for each entry into the AGESA API. Current code assumes only Callout would be relevant, which is not quite the case. Change-Id: I0cc66d01d62fa8dc6bb7c9f9fab6fa4753827554 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/27111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-06-14src: Get rid of unneeded whitespaceElyes HAOUAS
Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14stoneyridge: Increase SMM stack size to 2KRaul E Rangel
GSMI Set Event Log is taking more than 1K in stack. This causes the stack to overflow into the adjacent stack. This has the side effect of causing any CPU waiting for the SMI handler to complete to crash when the lock is unlocked because the return pointer has been smashed. BUG=b:80539294 TEST=built on grunt and tested by running `halt` from the OS. Change-Id: Ib170c7d03909ef3d20831726b285178a75007b06 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27033 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-14AGESA binaryPI: Drop RAMBASE and RAMTOPKyösti Mälkki
With platforms moved to RELOCATABLE_RAMSTAGE, these overrides no longer have a meaning. Overrides existed because AGESA ramstage did not fit within the default 1 MiB of RAMTOP - RAMBASE, when placed low. Change-Id: I0185875dc550de74877c94f36128d5979e5553d6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26813 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-14AGESA binaryPI: Drop tests for LATE_CBMEM_INITKyösti Mälkki
Change-Id: I4571e8b560559b3d7afe429eca8caa1512e244a8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-13amd/stoneyridge: Add early MTRR setup for new calloutsMarshall Dawson
Enable the two ranges to be used for the new callouts, AgesaHeapRebase and AgesaGetHeapBaseInDram. TEST=Boot grunt w/experimental blob, try different addresses BUG=b:74518368 Change-Id: Ic7716794dc7d75f849e6e062865d6efbeb4292df Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/26147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-13amd/pi: Add AgesaHeapRebase calloutMarshall Dawson
Implement an optional callout for AgesaHeapRebase which allows AGESA to override any internal hardcoded heap addresses. Designate a region in CAR that may be used for pre-mem heap and return that address before DRAM is configured. After DRAM is up, the address in cbmem is returned. TEST=Boot grunt with patchstack and experimental blob BUG=b:74518368 Change-Id: Ieda202a6064302b21707bd7ddfabc132cd85ed45 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/25458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-13amd/pi: Add GetTempHeapBase calloutMarshall Dawson
Implement a new AGESA callout that may be used to find the correct temporary location in DRAM to store heap data. Near the end of AmdInitPost, AGESA migrates its heap from a CAR-based location to a temporary region. Once cbmem has been established, the heap will be relocated again in AmdInitEnv from the temp location to the final one. This patch does not materially affect the behavior of AGESA's heap management. It only puts coreboot in control of the location. Future work may refactor the copying. TEST=Boot grunt with patchstack and experimental blob BUG=b:74518368 Change-Id: Ibc5cc988e3e80d78f50cf0195e952b657141e570 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/26146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-13soc/amd/stoneyridge/acpi.c: Create GPIO acpigen proceduresRichard Spiegel
There are some acpigen functionality that have not been implemented. They are defined as week within acpigen.c, in order to not break the build. This adds stoneyridge specific versions. BUG=b:79546790 TEST=Build grunt with added debug code to gpio_lib.asl. Boot to OS, activate ACPI debug, activate S3 stress test. Interrupt stress test, do a "cat /var/log/messages" saving the serial output. Examine the serial output, see added debug code showing action taken. Confirm action by reading proper register. Debug code removed. Change-Id: I9062d889f828a3175b89e6f4a3659ebbf90eac68 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-13soc/amd/stoneyridge/southbridge.c: Fix saving _SWS parametersRichard Spiegel
PM1 and GPE0 are being stored directly to NVS, when actually what should be saved is the index of the bit responsible for waking. Fix the procedures and add definitions to the actual IO addresses to be read when recording status and enable registers. BUG=b:75996437 TEST=Build and boot grunt. Once in OS, execute a sleep and a wake. See the message indicating which indexes are being save in NVS for _SWS. Try sleep stress test, verify that the index is different from that of power button. Change-Id: I8bafc7bb7dd66e7f0eb8499e748535bbdcac5f53 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-12soc/amd/stoneyridge/acpi: Create a GPIO libraryRichard Spiegel
There are some acpigen functionality that have not been implemented. In order to implement them, ACPI GPIO functions to read and write to the control MMIO of a particular pin is needed. So as a preliminary task to implementing acpigen functions, create a library with functions to be accessed by acpigen generated ACPI code. BUG=b:79546790 TEST=Build grunt, more tests with commit 0f2acbd6b1. Change-Id: I21c014b7f2698dd9193dae3113b18ee2a7303bcf Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-12stoneyridge: Move agesa out of bootblockRaul E Rangel
This is Garrett's patch with a bit of cleanup. BUG=b:65442212 TEST=Was able to boot, suspend and resume on grunt. Change-Id: I55959b59a4e60b679d959ebd77de27e5d454f5f7 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/26478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-08amd/stoneyridge: Set SCI_MAP for SCI enabled GPIOsDaniel Kurtz
By default we use a 1:1 mapping between GEVENT bits and the corresponding SCI_MAP entry. However, we still must program the SCI_MAP entries with the GEVENT number. BUG=b:109759838 TEST=(1) powerd_dbus_suspend (2) move finger on touchpad for ~1 second => system resumes from S3 Change-Id: Ie7be45264f9bfec56efc47a03071fdb924d16b6a Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26930 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-06arch/x86: Make RELOCATABLE_RAMSTAGE the defaultKyösti Mälkki
No need to provide an option to try disable this. Also remove explicit ´select RELOCATABLE_MODULES' lines from platform Kconfigs. Change-Id: I5fb169f90331ce37b4113378405323ec856d6fee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04src/soc: Get rid of whitespace before tabElyes HAOUAS
Change-Id: Ia024fb418f02d90c38b9a35ff819c607b9ac4965 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04soc/{amd,intel}: Use postcar_frame_add_romcache()Nico Huber
Change-Id: Iee816628ac3c33633f5f45798562a4ce49493a65 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-01soc/amd/stoneyridge: Add ACPI device name lookupMarc Jones
Add the ACPI devices defined in ASL to the soc_acpi_name() lookup function. BUG=b:80280671 TEST=Add ACPI method to specific GPP bridge. Boot and verify method with ACPI dump. Change-Id: I5117e0d39db831364173c9c61ccdab6e34f18c59 Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/26698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-05-31soc/{amd,intel}: Use CACHE_ROM_(BASE|SIZE)Nico Huber
Boards could choose a high ROM_SIZE that would result in an MTRR config that conflicts with other resources. Thus, always use the filtered CACHE_ROM_SIZE. Change-Id: I66d36b84ce49c1cb98cb36a4731977baaedf3225 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26575 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-29src/soc: Add and update license headersMartin Roth
This change adds and updates headers in all of the soc files that had missing or unrecognized headers. After this goes in, we can turn on lint checking for headers in all soc directories. Change-Id: I8b34dcd10c692f1048bd8d6c0fe3bfce13d54967 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-05-27grunt: Wire up the EC SMI handlerRaul E Rangel
This won't actually get called yet since the GPIO pin has not been configured as SMI. BUG=b:80295434 TEST=grunt: Made sure events could be processed. Change-Id: I189e26196e4543b3e34bff5d9df8566eff07d585 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/26546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-05-27amd: Don't call halt() when in SMMRaul E Rangel
This copies what Intel does. BUG=b:80295434 TEST=grunt: Made sure that the S5 SMI interrupt gets fired. Change-Id: I7874824cad01054c6bdeff12d248e671f27be030 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/26545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-27stoneyridge GPIO: Create and use PAD_INT for interrupt pinsRichard Spiegel
The default interrupt control for GPIO pins within stoneyridge is for edge triggered, high. However, sometimes these need to change, or maybe the interrupt needs to be reported or delivered. This was the case of platform grunt, where the interrupt related bits were being changed afterwards. Ideally all the bits should be programmed through the same procedure. Create several PAD_INT definitions (for general configuration, for trigger configuration and for interrupt type configuration) and change function sb_program_gpios() to accept the output from PAD_INT_XX and program all the necessary bits while keeping compatibility with other PAD_XX definitions. BUG=b:72875858 TEST=Add code to report GPIO and interrupt configuration, build grunt and record a baseline. Add new code, rebuild grunt and record a test output. Compare baseline against test, there should be no change in GPIO or interrupt programming. Remove code that reports GPIO/interrupt configuration. Change-Id: I3457543bdf64ec757fd82df53c83fdc1d03c1f22 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-25soc/amd/stoneyridge: Increment boot_count on non-S3 bootsDaniel Kurtz
Increment the boot_count from romstage when not resuming from S3. BUG=b:80266624 TEST=firmware_EventLog TEST=boot, then: mosys eventlog list | grep boot 1 | 2018-05-24 16:51:42 | System boot | 1 reboot mosys eventlog list | grep boot 1 | 2018-05-24 16:51:42 | System boot | 1 6 | 2018-05-24 16:52:34 | System boot | 2 Change-Id: Ideec9da809e494fb0ea073f648540285972f8238 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/26525 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-25soc/amd/stoneyridge: Record ACPI Wake events in ELOGDaniel Kurtz
We are already reporting the Wake source, but we must also report the ACPI wake itself. BUG=b:79865267 TEST=firmware_EventLog Change-Id: Id26dff46379800a63ab9b77f135d23c6382f77e6 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/26522 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-23mb/google/kahlee/dsdt.asl: Add method _SWSRichard Spiegel
_SWS is the recommended method of wake source retrieval. Now that PM1I and GPEI are available at NVS, add the method _SWS to kahlee/grunt ACPI code. BUG=b:76020953 TEST=Build grunt Change-Id: I5930438af40e6f9177462582cafb65401d9c60f4 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-23stoneyridge: Store wake parameters in NVSRichard Spiegel
ACPI _SWS needs information on PM1 and ACPI events (though events can be read directly). Unfortunately PM1 is cleared in normal path and in resume path. Save PM1 and ACPI events in NVS to be accessed by ACPI _SWS. BUG=b:75996437 TEST=Build and boot grunt recording serial. Run suspend stress test, after 3 resumes closed file and examined for the message indicating what was being saved to NVS. Two different path, normal boot (first boot) and resume path had different PM1. Change-Id: If3b191854afb27779b47c3d8d9f5671a255f51b5 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26208 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-23soc/amd/common/block/pci: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I82089475eb43d58303d1091f35aee06f1f04b4a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-05-23soc/amd/stoneyridge/: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I84fbc90b2a81fe5476d659716f0d6e4f0d7e1de2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-05-22amd/stoneyridge: Increase SMM reserved memoryMarshall Dawson
Add 64KB to the reserved memory used for stage_cache. This corrects an error observed when using a debug build of the AGESA blob. Messages on initial boot AGESA: Saving stage to cache Error: Can't add stage_cache 57a9e101 to imd and during resume AGESA: Loading stage from cache Error: Can't find stage_cache 57a9e101 in imd TEST=boot/suspend/resume Grunt with debug and release builds BUG=b:79154155 Change-Id: I3f27059fcef37e335d0301142ba4dedb3809e369 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/26386 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-22bootblock: Allow more timestamps in bootblock_main_with_timestamp()Julius Werner
This patch adds more parameters to bootblock_main_with_timestamp() to give callers the opportunity to add additional timestamps that were recorded in the platform-specific initialization phase. Change-Id: Idf3a0fcf5aee88a33747afc69e055b95bd38750c Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/26339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-19cpu/x86: Add support to run function on single APSubrata Banik
This patch ensures that user can select a specific AP to run a function. BUG=b:74436746 BRANCH=none TEST=Able to run functions over APs with argument. Change-Id: Iff2f34900ce2a96ef6ff0779b651f25ebfc739ad Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26034 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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