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2020-06-04soc/amd/picasso: fix iomap for ACPI_PMKangheui Won
offsets for ACPI_PM are incorrectly configured for picasso SoC. Especially incorrect ACPI_PM_TMR_BLK makes kernel to spend 10 sec for trying to testing it on wrong address. Fix them to correct offset with hack for GPE0_BLK. BUG=b:147044624 TEST=build and boot on trembyle; PM Timer error is gone Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I6adf71479c30f5b6751a21edc4bfa311ddbef5ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/41128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-03soc/amd: Use mp_cpu_bus_init()Kyösti Mälkki
Change-Id: Ia4508a9a087e3996ef7667280f8e2788421e5700 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-03soc,southbridge/amd: Remove some explicit zero-initializersKyösti Mälkki
Change-Id: I263c159fe4b7757dd5abfc0d6248e45b749df980 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-03soc/amd/picasso/acpi: Add missing eMMC deviceRaul E Rangel
BUG=b:154756391 TEST=Boot trembyle and see that /dev/mmcblk1 now exists Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ica83b78a7ab081d9eac9f5e267b2904dcde0b283 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-03soc/amd/picasso/acpi: Remove hardcoded FCH IRQ numbersRaul E Rangel
Modify the FCH ACPI devices to query the PCI IRQ mapping registers for their current IRQ numbers. BUG=b:139429446, b:154756391 TEST=Boot trembyle and see that I2C and UART devices are finally functional. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I8f2035f74240ead4089ff4d503dfbeb447cf8de4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-02soc/amd/picasso: Install AGESA ACPI tablesMatt Papageorge
AGESA FSP provides additional ACPI tables that are required. BUG=b:133337564, b:153675915 TEST=Boot trembyle to OS and dump ACPI tables. ACPI: added table 2/32, length now 44 ACPI: * MCFG ACPI: added table 3/32, length now 48 ACPI: * TPM2 TPM2 log created at 0xcc513000 ACPI: added table 4/32, length now 52 ACPI: * MADT ACPI: added table 5/32, length now 56 current = cc635af0 Searching for AGESA FSP ACPI Tables ACPI: * SSDT (AGESA). ACPI: added table 6/32, length now 60 ACPI: * CRAT (AGESA). ACPI: added table 7/32, length now 64 ACPI: * ALIB (AGESA). ACPI: added table 8/32, length now 68 ACPI: * IVRS (AGESA). ACPI: added table 9/32, length now 72 ACPI: * HPET ACPI: added table 10/32, length now 76 Copying initialized VBIOS image from 0x000c0000 ACPI: * VFCT at cc63ca30 ACPI: added table 11/32, length now 80 ACPI: done. ACPI tables: 102048 bytes. [ 0.042326] ACPI: Early table checksum verification disabled [ 0.048621] ACPI: RSDP 0x00000000000F0000 000024 (v02 COREv4) [ 0.055011] ACPI: XSDT 0x00000000CC6310E0 00007C (v01 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.064506] ACPI: FACP 0x00000000CC634850 000114 (v06 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.073998] ACPI: DSDT 0x00000000CC631280 0035CF (v02 COREv4 COREBOOT 00010001 INTL 20200110) [ 0.083488] ACPI: FACS 0x00000000CC631240 000040 [ 0.088623] ACPI: SSDT 0x00000000CC634970 00103D (v02 COREv4 COREBOOT 0000002A CORE 20200110) [ 0.098114] ACPI: MCFG 0x00000000CC6359B0 00003C (v01 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.107606] ACPI: TPM2 0x00000000CC6359F0 00004C (v04 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.117100] ACPI: APIC 0x00000000CC635A40 0000A6 (v03 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.126592] ACPI: SSDT 0x00000000CC635AF0 00119C (v01 AMD AMD CPU 00000001 AMD 00000001) [ 0.136082] ACPI: CRAT 0x00000000CC636C90 000810 (v01 AMD AMD CRAT 00000001 AMD 00000001) [ 0.145573] ACPI: SSDT 0x00000000CC6374A0 005419 (v02 AMD AmdTable 00000002 MSFT 02000002) [ 0.155064] ACPI: IVRS 0x00000000CC63C8C0 000126 (v02 AMD AMD IVRS 00000001 AMD 00000000) [ 0.164556] ACPI: HPET 0x00000000CC63C9F0 000038 (v01 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.174047] ACPI: VFCT 0x00000000CC63CA30 00D469 (v01 COREv4 COREBOOT 00000000 CORE 20200110) Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic1e87c0f7a7c736592dd8c5c6765ef9a37ed7a40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41804 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02src: Remove redundant includesElyes HAOUAS
<types.h> is supposed to provide <commonlib/bsd/cb_err.h>, <stdbool.h>,<stdint.h> and <stddef.h>. So remove those includes each time when <types.h> is included. Change-Id: I886f02255099f3005852a2e6095b21ca86a940ed Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-02src: Remove duplicated includesElyes HAOUAS
Change-Id: If8c7e26ebd954b19bfb8766b26570c6865ad255e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41676 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02soc/amd/picasso: Remove unused 'include <romstage_handoff.h>'Elyes HAOUAS
Change-Id: I07100361705ce421131b8a5d772cb5ba2d8722ff Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41672 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02src: Remove unused 'include <bootstate.h>'Elyes HAOUAS
Change-Id: I54eda3d51ecda77309841e598f06eb9cea3babc1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-02src: Remove unused '#include <timer.h>'Elyes HAOUAS
Change-Id: I57e064d26b215743a1cb06bb6605fc4fe1160876 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41491 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02src: Remove unused '#include <cpu/x86/lapic.h>'Elyes HAOUAS
Also, replace 'lapic.h' by 'lapic_def.h' in 'soc/intel/braswell/northcluster.c'. Change-Id: I71cff43d53660dc1e5a760ac3034bcf75f93c6e7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41489 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-29soc/amd/picasso: Enable FSP compressionFurquan Shaikh
This change enables LZMA compression for both FSP-M and FSP-S. This results in significant savings in the FSP size in each CBFS: cbfstool firmware/image-trembyle.bin print -r COREBOOT | grep fsp fspm.bin 0x9cdc0 fsp 132404 LZMA (720896 decompressed) fsps.bin 0xbdfc0 fsp 86146 LZMA (327680 decompressed) LZ4 works too, but the savings are smaller as compared to LZMA: cbfstool firmware/image-trembyle.bin print -r COREBOOT | grep fsp fspm.bin 0x9cdc0 fsp 189530 LZ4 (720896 decompressed) fsps.bin 0xcbfc0 fsp 118952 LZ4 (327680 decompressed) BUG=b:155322763,b:150746858,b:152909132 TEST=Verified that Trembyle boots to OS. No FSP-M or FSP-S errors in boot logs. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ie5e4d58e671e936aa525d3000f890e9e5ae45ec3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-29soc/amd/picasso: Relocate FSP-M to address in DRAMFurquan Shaikh
On Picasso, DRAM is up by the time FSP-M runs. This change relocates FSP-M binary to a specific address (0x90000000) in DRAM. Currently, this address is randomly chosen to ensure it does not overlap any of the other stages. Once we have a unified memory map set up for Picasso, this address can be updated along with it. BUG=b:155322763,b:150746858,b:152909132 Change-Id: I1a49765f00de9f97fa3dbd5bc288a3ed0d7087f6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41828 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28soc/amd/picasso/soc_util: add comment on socket detection problemsFelix Held
At least some Pollock engineering samples return FP5 socket type while they are in fact FT5 socket type. Change-Id: I06a19c19374532bfb367fc15c734707d8c7f65a3 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41796 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28soc/amd/picasso/soc_util: remove unused functionsFelix Held
soc_is_pollock() and soc_is_picasso() aren't used by any mainboard or soc code. The same fuctionality is still provided by get_soc_type(). Change-Id: I046b4925bfeb4b31d11e2548ac87b7bbca0f6475 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41795 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-27soc/amd/picasso/smu: only print time for actual command executionFelix Held
When waiting for the SMU to be ready to accept a new command, the time spent waiting shouldn't be printed as command execution time. Also fix the time unit in the print statement. Change-Id: I6b97b11cd9efae7029779ee2096d4f2224cecd72 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-27soc/amd/picasso: Use SMU to put system into S3Marshall Dawson
Send a message to the SMU to turn off the system power. SMU will take the proper final steps based on PmControl[SlpTyp]. BUG=b:153264473 TEST=verify system can enter S3 Change-Id: I3c0d98110c12963aa6fef5d176fd9acaa7ed9f26 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/2140471 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41626 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-27soc/amd/picasso: Add generic SMU service requestMarshall Dawson
Add a new feature that allows messages to be sent to the SMU. The offsets of the PCI config index/data indirect registers have been documented for prior generation devices. The index/data pair is used to access a command register, a response, and six argument values. BUG=b:153264473 TEST=Verify service can be used to take the system into S3 Change-Id: Ide431aa976cb2f8bdc248cb08aa0724a9596ac5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://chromium-review.googlesource.com/2161796 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-27soc/amd/picasso/Makefile: Change APCB_magic.bin locationRaul E Rangel
The APCB_magic.bin lives in amd_blobs, not blobs. BUG=b:157140753 TEST=Boot trembyle to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib082a8e7fc631ca7145b0b77e49ea0cbf99dff41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41734 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-27soc/amd/picasso: add and use CPUIDs for older steppingsFelix Held
Change-Id: Ibe768ef7cd714c17fd5a296d9a3e5f963ae0ef01 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41641 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-27soc/amd/picasso: rewrite soc_utilFelix Held
This adds proper RV2 silicon and Dali SKU detection using both CPUID information and some bits from silicon_id in the Picasso misc data HOB that FSP-M stores in memory. BUG=b:153779573 Change-Id: I589be3bdac4b94785e6ecacf55235be4ad5673d9 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-26soc/amd/picasso: Use C00n for CPU ACPI stringMarshall Dawson
Match the path generated by AGESA. Add more PPKG packages. TEST=Verify that "\_PR.C00n" AE_NOT_FOUND errors go away BUG=b:145013057 Change-Id: I82587648d37c0be885991f2e5741d9f874d6a2eb Signed-off-by: Marshall Dawson <marshall.dawson@amd.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/1937788 Reviewed-by: Martin Roth <martinroth@chromium.org> Commit-Queue: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-05-26soc/amd/picasso: Give the mainboard the ability to modify the MADT tableRaul E Rangel
By default legacy ISA IRQs use edge triggering. Depending on what devices are used the IRQ types might need to be changed. We add a setting to the device tree to allow the mainboard to configure the IRS IRQs. BUG=b:145102877 TEST=Booted trembyle and was able to use the keyboard. Change-Id: Ie95e8cc7ca835fb60bee8f10d5f28def6c2801dc Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2033493 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-24soc/amd/picasso/include/cpu: add Raven1 CPUIDFelix Held
Change-Id: Iaf848a68dc50c2af1e32b996f09296aaea935459 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41628 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-21soc/amd/common/block/gpio: add API for gpio override tablePeichao Wang
This function adds support for gpio_configure_pads_with_override which: 1. Takes as input two GPIO tables -- base config table and override config table 2. Configures each pad in base config by first checking if there is a config available for the pad in override config table. If yes, then uses the one from override config table. Else, uses the base config to configure the pad. BUG=b:153456574 TEST=Build and boot dalboz BRANCH=none Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I07bfe82827d1f7aea9fcc96574d6deab9e91d503 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2153423 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41576 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-21soc/amd/picasso/chip.c: Generate ACPI nodes for PCI Bridge A and BRaul E Rangel
This node is required so we can add child ACPI nodes. BUG=b:147042464 TEST=Boot trembyle and confirm Bus A has a firmware node $ cat /sys/bus/pci/devices/0000\:00\:08.1/firmware_node/path \_SB_.PCI0.PBRA Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I18144a69ed28a913bc9a2523d69edf84a1402e7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/41546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-21soc/amd/picasso/pci_devs: Update pci_devs.h with correct valuesFurquan Shaikh
This is a squash of the following commits. The original values were wrong, and had confusing naming. soc/amd/picasso: Get rid of *_DEVID from pci_devs.h Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: I203449499840bf0a6df8bd879fb7d2e75a16b284 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2153714 src/amd/picasso: Update PCI bridge devices Orignal-Change-Id: I1fa9d52ce113eacdc5c9ba31ab46b6428a7d6ca9 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Zork: Reorganizing ACPI and adding PCI bridge configs Signed-off-by: Pranay Shoroff <pshoroff@google.com> Original-Change-Id: I1e2095567525f302dfd0bce8e39001250523180b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2063536 soc/amd/picasso: Fix soc_acpi_name() to use devfn instead of devid Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: I2486e7e0059e0528f53d5a158c9328636563fe93 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2153712 BUG=b:147042464 TEST=Build trembyle and boot to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I91bf7f9edcddf03027f8fdcaadf4e290ece10df5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-05-21soc/amd/picasso: Add APOB NV back for non-S3Marshall Dawson
New information indicates the PSP expects the APOB NV region populated for all types of boot, and this is not a feature only used for S3. Switch over to using the MRC_CACHE flash region. Remove the Kconfig symbols for the APOB_NV base and size. Override the MRC_CACHE_SETTINGS_CACHE_SIZE to ensure the default maintains the minimum required size. Use the generated (or mainboard-specified) fmap.fmd file as an input for amdfwtool and properly match the flash region. Change the original naming for the APOB destination, which matched the PSP spec's field name, to PSP_APOB_DESTINATION. This should be more intuitive for a source code reader. The APOB address is the location in DRAM where the PSP puts its output block. BUG=b:147042464, b:153675914 TEST=Boot trembyle Original-Change-Id: Ia5ba8646deec2bd282df930f471738723063eef8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2080375 Original-Change-Id: I972d66f1817f86ff0b689f011c0c44c3fe7c8ef7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2053312 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I4550766ece462b65a6bfe6f1b747343e08e53fe5 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-21soc/amd/picasso/soc_util: change return type of soc_is_*Felix Held
All callers just check for zero/non-zero. Change-Id: I795763ce882d879d12c97b71e7a0b35423378c36 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-21soc/amd/picasso/include/soc_util: add include guardsFelix Held
Change-Id: I2de16eaa88baace28afa30345b7762353a48ab87 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41558 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-21soc/amd/picasso/southbridge: add missing soc/i2c.h includeFelix Held
soc/i2c.h gets included indirectly via chip.h and removing the chip.h in 73716d0e924080ea32274a265a8de04e009c3676 broke the build. chip.h got added back, but including soc/i2c.h directly fixes the underlying issue. Change-Id: Ic84f7b6b4447b7c335a51dc604daf8924851e555 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-20soc/amd/picasso: Add pcie root complex driverMarshall Dawson
* Declare memory and reserved areas using HOBs for regions above top of low memory. * Copy northbridge_fill_ssdt_generator from stoneyridge. BUG=b:147042464 TEST=Boot trembyle and see PCI resources in the log: PCI: 00:00.0 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 2 PCI: 00:00.0 resource base 100000 size cd700000 align 0 gran 0 limit 0 flags e0004200 index 3 PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:00.0 resource base ce000000 size 2000000 align 0 gran 0 limit 0 flags f0004200 index 4 PCI: 00:00.0 resource base 100000000 size 12f340000 align 0 gran 0 limit 0 flags e0004200 index 5 PCI: 00:00.0 resource base 22f340000 size cc0000 align 0 gran 0 limit 0 flags f0004200 index 6 PCI: 00:00.0 resource base cd800000 size 800000 align 0 gran 0 limit 0 flags f0004200 index 7 PCI: 00:00.0 resource base cd7fe000 size 2000 align 0 gran 0 limit 0 flags f0004200 index 8 PCI: 00:00.0 resource base cc7fe000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index 9 PCI: 00:00.0 resource base 1090000 size b0000 align 0 gran 0 limit 0 flags f0004200 index a Change-Id: I44a4a97765151fbcfe4c5d8de200e3e015aaaf2e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34424 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20soc/amd/picasso: Add Kconfig option for the PSP bootloader filenameMartin Roth
Add option to change bootloader file. BUG=b:149934526 TEST=Change option and verify new bootloader file is used. Using the amd_blobs I can only boot using PspBootLoader_test_RV_dbg.sbin. Change-Id: Ib6597f7d4ffa0d48aead6974bd7111c987418f20 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2067598 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-20soc/amd/picasso/acpi: Improve PCI Interrupt Link DevicesRaul E Rangel
The PCI interrupt devices were only partially implemented. * Lacked support for _DIS to disable the bus. Something the kernel does while booting. * Lacked support for APIC vs PIC. This means the devices can only be used when using the PIC. By looking at the PMOD variable we can handle both PIC and APIC. This means we can stop hard coding the PCI interrupt numbers in the ACPI tables. * I removed INT[E-H] since they are not used. BUG=b:139429446, b:147042464 BRANCH=none TEST=Boot with both the APIC and PIC and saw that the link devices work as expected: PIC MODE: [ 1.959345] ACPI: PCI Interrupt Link [IRQA] (IRQs 1 3 4 5 *6 7 8 9 10 11 12 14 15) [ 2.007344] ACPI: PCI Interrupt Link [IRQB] (IRQs 1 3 4 5 *6 7 8 9 10 11 12 14 15) [ 2.056344] ACPI: PCI Interrupt Link [IRQC] (IRQs 1 3 4 5 6 7 8 9 10 11 12 *14 15) [ 2.104344] ACPI: PCI Interrupt Link [IRQD] (IRQs 1 3 4 5 6 7 8 9 10 11 12 14 *15) [ 13.752676] PCI Interrupt Link [IRQA] enabled at IRQ 6 [ 13.816755] PCI Interrupt Link [IRQD] enabled at IRQ 15 [ 27.788798] PCI Interrupt Link [IRQB] enabled at IRQ 6 [ 27.852873] PCI Interrupt Link [IRQC] enabled at IRQ 14 APIC MODE: [ 19.311764] ACPI: PCI Interrupt Link [IRQA] (IRQs *16 17 18 19 20 21 22 23) [ 19.374765] ACPI: PCI Interrupt Link [IRQB] (IRQs 16 *17 18 19 20 21 22 23) [ 19.438770] ACPI: PCI Interrupt Link [IRQC] (IRQs 16 17 *18 19 20 21 22 23) [ 19.501764] ACPI: PCI Interrupt Link [IRQD] (IRQs 16 17 18 *19 20 21 22 23) [ 34.719072] PCI Interrupt Link [IRQA] enabled at IRQ 23 [ 34.798994] PCI Interrupt Link [IRQD] enabled at IRQ 22 [ 66.469510] PCI Interrupt Link [IRQB] enabled at IRQ 21 [ 66.542395] PCI Interrupt Link [IRQC] enabled at IRQ 20 Change-Id: I1bb84813b65c89b4b5479602be3e9a9fedb7333d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2095683 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-05-20soc/amd/picasso/acpi: Move _PIC method to root namespaceRaul E Rangel
The _PIC method sets the interrupt model (PIC or APIC). It needs to be defined at the root level for the kernel to find it. Previously this method was never getting called, so we were always stuck in APIC mode. BUG=b:139429446, b:147042464 BRANCH=none TEST=Saw the method getting called [ 1.251774] ACPI Debug: "PIC MODE: 0000000000000001" Change-Id: Idd5e9646df8d56e7cbec2be8b4016c36d81e5fb8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2095682 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-05-20soc/amd/picasso/soc_util: use socket type detectionFelix Held
Remove the Kconfig options for per board socket type selection and use the runtime detection instead. Change-Id: I82cf922661c24e2a529fa4927893727b643660e3 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41518 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20soc/amd/picasso/soc_util: add socket type detection and printingFelix Held
Change-Id: I643a4c5f8a42a5fb0603a1a049545b57d16493a6 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41517 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-19soc/amd/picasso/romstage: removed unused includeFelix Held
Change-Id: I550599ae5ef9875ce820a4534d21439ff2027585 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-18soc/amd/picasso: add telemetry settingChris Wang
Add telemetry setting for SDLE testing BUG=b:147570294 TEST=Build Morphius and check the setting was been applied Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If4bb75eeaaa68b2c5a6a36c28c34fb338be65851 Reviewed-on: https://chromium-review.googlesource.com/2056885 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Tested-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-18soc/amd/picasso/romstage: add missing types.h includeFelix Held
Change-Id: I26f15e7bd2f65e94ed1c2771bd8504114bfcda48 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-18soc/amd/picasso/Makefile: Use apcb_tool to generate APCBs from SPDsRaul E Rangel
BUG=b:147042464 TEST=Boot trembyle to OS Signed-off-by: Rob Barnes <robbarnes@google.com> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ife48d5268230f70c6a6f4a56c1f0d05b6c924891 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41381 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18soc/amd/picasso: Switch to using amd_blobsRaul E Rangel
BUG=b:147042464 TEST=build trembyle and boot to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie6ac8b0701ac27733dd9724873664f5f17fcfa29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-18soc/amd/picasso: only link soc_util in ramstageFelix Held
No code that was or will be upstreamed uses functionality from soc_util in romstage, so only compile and link it for ramstage. This also allows to fix the SoC type detection in a follow-up patch using information that FPS-M will be providing in a HOB. BUG=b:153779573 Change-Id: If96e53608eadd562f6de5a0c370b89e84e43d049 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-18Remove new additions of "this file is part of" linesElyes HAOUAS
Change-Id: I96dfa5b531842afcf774dd33c2dfa532b5d329c6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-05-18soc/amd/picasso: Set VERSTAGE_ADDR for picassoRaul E Rangel
By default ROMSTAGE_ADDR and VERSTAGE_ADDR are set to 0x2000000. This causes problems in a non-xip environment because when verstage loads romstage, it overrides it's memory. So pick a different offset for verstage. BUG=b:147042464 TEST=Boot verstage on trembyle and see OS boot. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I2464db6f3769bd23d250588b341d1c9e44f10d21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41367 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-14soc/amd/stoneyridge: add resources during read_resources()Furquan Shaikh
The chipset code was incorrectly adding memory resources to the domain device after resource allocation occurred. It's not possible to get the correct view of the address space, and it's generally incorrect to not add resources during read_resources(). This change fixes the order by adding resources during read_resources(). Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I532f508936d5ec154cbcb3538949316ae4851105 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41369 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13soc/amd/picasso: Enable eSPI capability for PicassoFurquan Shaikh
This change selects SOC_AMD_COMMON_BLOCK_HAS_ESPI which enables the capability for using eSPI on Picasso. Additionally, it also calls espi_setup() and espi_configure_decodes() if mainboard enables use of eSPI and skips LPC decodes in that case. BUG=b:153675913,b:154445472 Change-Id: I4876f1bff4305a23e8ccc48a2d0d3b64cdc9703d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-13soc/amd/picasso: Use lpc_early_init() from common lpc driverFurquan Shaikh
This change uses lpc_early_init() for enabling and configuring LPC using the common block LPC driver. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I65784b481ae598bf3a85392ae4fe281aac974097 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41273 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13soc/amd/common/block: Add support for configuring eSPI connection to slaveFurquan Shaikh
This change adds a helper function espi_setup() which allows SoCs to configure connection to slave. Most of the configuration is dependent upon mainboard settings in espi_config done as part of the device tree. The general flow for setup involves the following steps: 1. Set initial configuration (lowest operating frequency and single mode). 2. Perform in-band reset and set initial configuration since the settings would be lost by the reset. 3. Read slave capabilities. 4. Set slave configuration based on mainboard settings. 5. Perform eSPI host controller configuration to match the slave configuration and set polarities for VW interrupts. 6. Perform VW channel setup and deassert PLTRST#. 7. Perform peripheral channel setup. 8. Perform OOB channel setup. 9. Perform flash channel setup. 10. Enable subtractive decoding if requested by mainboard. BUG=b:153675913 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I872ec09cd92e9bb53f22e38d2773f3491355279e Reviewed-on: https://review.coreboot.org/c/coreboot/+/41272 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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