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2020-04-16soc/amd/common/psp: refactor psp_print_cmd_status parametersFelix Held
psp_print_cmd_status only needs data from the mbox buffer header and not the whole buffer. This avoids type casts when the buffer type isn't mbox_default_buffer. BUG=b:153677737 Change-Id: I8688b66fefe89fc4f3ce2207d4360ceb2dbaef12 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40412 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-16soc/amd/picasso: Notify PSP system is going to sleep stateMarshall Dawson
BUG=b:153677737 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ic72bd5f5710181ca4f282feba5f7531b098c907a Reviewed-on: https://review.coreboot.org/c/coreboot/+/40298 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-16soc/amd/common/psp: Add notify_sx_infoFelix Held
Add the command to tell the PSP the system is going to a sleep state. BUG=b:153677737 Change-Id: I50da358e1f8438b46dbb1bda593becf6dd4549ea Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/2020367 Reviewed-on: https://chromium-review.googlesource.com/2110764 Reviewed-on: https://chromium-review.googlesource.com/2121159 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-16soc/amd/psp: Add SmmInfo commandMarshall Dawson
Implement the MboxBiosCmdSmmInfo function to inform the PSP of the SoC's SMM configuration. Once the BootDone command is sent, the PSP only responds to commands where the buffer is in SMM memory. Set aside a region for the core-to-PSP command buffer and the PSP-to-core mailbox. Also add an SMM flag, which the PSP expects to read as non-zero during an SMI. Add calls to soc functions for the soc to populate the trigger info and register info (v2 only). Add functions to set up the structures needed for the SmmInfo function in Picasso support. Issue a SW SMI, and add a new handler to call the new PSP function. BUG=b:153677737 Change-Id: I10088a53e786db788740e4b388650641339dae75 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-15soc/amd/picasso: Add common PSP supportMarshall Dawson
Add a new psp.c file so the base address can be determined, and select the common/block/psp feature. BUG=b:153677737 Change-Id: I322fd11a867a817375ff38a008219f9236c4f2ea Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/2020368 Tested-by: Eric Peers <epeers@google.com> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40296 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-15soc/amd/common/psp: add Kconfig description to interface versionFelix Held
BUG=b:153677737 Change-Id: I5b017dfc92563ec4f0a2edb24416d6b65587d9a3 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-15soc/amd/common/block/psp: move psp_load_named_blob to psp_gen1.cFelix Held
This function is only needed and valid for the 1st generation PSP interface used on stoneyridge. BUG=b:153677737 Change-Id: Ia1be09c32271fe9480a0acbe324c4a45d8620882 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-13acpi: Bump FADT to revision 6Patrick Rudolph
Some of the revision 4 FADT fields were already updated to ACPI spec revision 6, but not all of them. In addition the advertised FADT revision was 3. Implement all fields as defined in version 6 and bump the advertised FADT revision to 6. Also set all used access_size fields and x_gpe0_blk to sane values as Windows 10 verifies those fields starting with FADT revision 5. Fixes: https://ticket.coreboot.org/issues/109 Tested on Windows 10. Change-Id: Ic649040025cd09ed3e490a521439ca4e681afbbf Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-04-13soc/amd/common/psp: Split mailbox support into v1 and v2Marshall Dawson
Family 17h redefines the PSP command and status, and therefore the steps required to send commands via the mailbox. Convert the existing version into a v1 and add a v2. New Kconfig options allow the soc to choose v1 vs. v2. The v2 PSP begins responding to the mailbox command when the full bit range is written. Define the new mailbox as a union of a u32 and a structure. Additional PSP details may be found in the NDA publication (#55758) AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors Change the existing two soc functions that return pointers to void pointers. BUG=b:153677737 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4d358fdae07da471640856f57568059e9487f6a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-13soc/amd/picasso/soc_util: add TODO to Dali detectionFelix Held
Change-Id: I8ff5a9275d4cdf0049b63cc30b8a1cc376b50f80 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-10Replace DEVICE_NOOP with noop_(set|read)_resourcesNico Huber
`.read_resources` and `.set_resources` are the only two device operations that are considered mandatory. Other function pointers can be left NULL. Having dedicated no-op implementations for the two mandatory fields should stop the leaking of no-op pointers to other fields. Change-Id: I6469a7568dc24317c95e238749d878e798b0a362 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40207 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-10Drop unnecessary DEVICE_NOOP entriesNico Huber
Providing an explicit no-op function pointer is only necessary for `.read_resources` and `.set_resources`. All other device-operation pointers are optional and can be NULL. Change-Id: I3d139f7be86180558cabec04b8566873062e33be Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40206 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-08soc/amd/picasso: replace get_soc_config with config_of_socFelix Held
get_soc_config was a reimplementation of config_of_soc, so drop get_soc_config and cfg_util.c. Change-Id: I007c83cfe5063130c18819925844b6c643cf0232 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-08soc/amd/stoneyridge: replace get_soc_config with config_of_socFelix Held
get_soc_config was a reimplementation of config_of_soc. Change-Id: I73c6a84703e22d6778b830f4bb82419361c85ff7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-04-05soc/amd: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I22fffa0eab006be2bad4d3dd776b22ad9830faef Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-05Drop explicit NULL initializations from `device_operations`Elyes HAOUAS
Unmentioned fields are initialized with 0 (or NULL) implicitly. Beside that, the struct has grown over the years. There are too many optional fields to list them all. Change-Id: Icb9e14c58153d7c14817bcde148e86e977666e4b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40126 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-02Trim `.acpi_fill_ssdt_generator` and `.acpi_inject_dsdt_generator`Nico Huber
These two identifiers were always very confusing. We're not filling and injecting generators. We are filling SSDTs and injecting into the DSDT. So drop the `_generator` suffix. Hopefully, this also makes ACPI look a little less scary. Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: David Guckian Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-02soc/amd/common/psp: Move definitions into a private fileMarshall Dawson
Declutter psp.h by removing internal details the caller doesn't need to know. BUG=b:130660285 TEST: Verify PSP functionality on google/grunt Change-Id: I2fb0ed1d2697c313fb8475e3f00482899e729130 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/2020366 Tested-by: Eric Peers <epeers@google.com> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40015 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-02soc/amd/common/psp: Move early init to socFelix Held
The initialization code in common//psp is very specific to Family 15h. Move this to the stoneyridge directory. BUG=b:130660285 TEST: Verify PSP functionality on google/grunt Change-Id: Ice3d06d6437f59a529c26fc2359565c940d39482 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/2020365 Reviewed-by: Eric Peers <epeers@google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-02soc/amd/common/psp: Consolidate FW blob load functionsMarshall Dawson
The commands used in Family 15h for loading the SMU FW blobs out of flash had already been defined differently in Family 17h. To begin removing Family 15h dependencies from the common/psp, change the definitions of blob type to no longer match the Family 15h commands. Consolidate the two functions used for interpreting the command and applying the command into a single one. BUG=b:130660285 TEST: Verify PSP functionality on google/grunt Change-Id: Ic5a4926175d50c01b70ff9b10908c38b3cbe8f35 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/2020364 Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Raul E Rangel <rrangel@chromium.org> Tested-by: Eric Peers <epeers@google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-02soc/amd/common/psp: Make common function to print statusMarshall Dawson
Consolidate commands' printing of status into one static function. BUG=b:130660285 TEST: Verify PSP functionality on google/grunt Change-Id: Id8abe0d1d4ac87f6d4f625593f47bf484729906f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/2020363 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Eric Peers <epeers@google.com> Tested-by: Eric Peers <epeers@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39998 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-31security/vboot: relocate and rename vboot_platform_is_resuming()Bill XIE
After measured boot is decoupled from verified boot in CB:35077, vboot_platform_is_resuming() is never vboot-specific, thus it is renamed to platform_is_resuming() and declared in bootmode.h. Change-Id: I29b5b88af0576c34c10cfbd99659a5cdc0c75842 Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-03-30soc/amd/picasso: Add helper functions for finding SOC typeMartin Roth
We're running into more and more situations where we need to tell one SOC type from another, and instead of rewriting them every time, just add some helper functions to the picasso SOC directory. Change-Id: I24b73145cdfa80c09fbe036d1fb6079696c6d013 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/2051514 Reviewed-on: https://chromium-review.googlesource.com/2060904 Reviewed-on: https://chromium-review.googlesource.com/2060905 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-29soc/amd/picasso: Add and use CPUID defines for Picasso and Raven2Martin Roth
Change-Id: I35a1c404ff2f381d3d6bf4f2e4bbbf5429db38c3 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1961485 Reviewed-on: https://chromium-review.googlesource.com/2060905 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-29soc/amd/picasso: Add Kconfig option for chip footprintFelix Held
Pollock uses the FT5 footprint, so add the Kconfig option to allow us to differentiate the chips. Change-Id: Ia4663d38f1824786f14b6aa000adf27d64e70b5f Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/2051509 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Eric Peers <epeers@google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-25amd/common/acpi: move thermal zone to common locationMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I048d1906bc474be4d5a4e44b9c7ae28f53b49d5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-25acpi: correct the processor devices scopeMichał Żygowski
The ACPI Spec 2.0 states, that Processor declarations should be made within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated and is removed here. Additionally add processor scope patching for P-State SSDT created by AGESA, becasue AGESA creates the tables with processors in \_PR scope. TEST=boot Debian Linux on PC Engines apu2, check dmesg that there are no errors, decompile ACPI tables with acpica to check whether the processor scope is correct and if IASL does not complain on wrong checksum, run FWTS Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I35f112e9f9f15f06ddb83b4192f082f9e51a969c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39698 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-18soc/amd/picasso: Add CPUID of newer deviceMarshall Dawson
Add a new device (Family 17h Models 20h-2Fh) to the cpu driver. Change-Id: Id792533e60813b7509bacd6806f78cd8bba56e37 Signed-off-by: Marshall Dawson <marshall.dawson@amd.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1950713 Reviewed-by: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-18soc: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-03-17soc/amd/picasso: Set I2C clock reference to 150MHzMartin Roth
Picasso uses a 150MHz reference clock for the Designware I2C devices. This update allows us to get the correct speeds out. BUG=b:143885765 TEST=Trembyle has 400kHz I2C clock Change-Id: Ia888a74e51201b6c911e0e810f0535403204cf60 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1970656 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-17soc/amd/picasso: Remove unused defines from cpu.hMarshall Dawson
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I4ed3e7c82ef5808a0e96c07c16f4872f8ca3ec76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-17soc/amd/picasso: Move get_soc_config to common locationMarshall Dawson
Multiple files can eventually take advantage of the static function in i2c.c. Move get_soc_config() into a new common location for all to use. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: If5d9be2f74cde370979033365af2e355eb6d814e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-02soc/amd/picasso: Add PCI ID for Dali xHCIMarshall Dawson
soc//picasso is intended to be forward-compatible with the Dali APU, a Family 17h Models 20h-2Fh product. Add the one new device ID it has. See PPR document #55772 (still NDA only) for more information. Change-Id: I7e9b90bb00ae6f4a121f10b1467d2ca398ac860c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2020-02-24soc/amd/common/block/include/amdblocks: Fix typosElyes HAOUAS
Change-Id: I8363816a51c342935668545a8b39acce96ce4b2c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38980 Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-20soc/amd/stoneyridge: Remove TODO for file extensionsMarshall Dawson
The comment is no longer relevant. Perhaps the intention had been to modify the names of the files delivered from AMD in order to simplify Makefile.inc. AMD firmware is distributed via the new amd_blobs repo and the filenames match the blobs as they are released. Multiple Family 15h devices are supported by this directory and their SMU Firmwares do not all follow identical naming convention. Keep the existing functionality and reword the comment. BUG=b:120118850 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ifbf8e2286f34bc37a6178c37f8c412ec51ee02c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-17vboot: remove VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT optionJoel Kitching
With CL:1940398, this option is no longer needed. Recovery requests are not cleared until kernel verification stage is reached. If the FSP triggers any reboots, recovery requests will be preserved. In particular: - Manual requests will be preserved via recovery switch state, whose behaviour is modified in CB:38779. - Other recovery requests will remain in nvdata across reboot. These functions now only work after verstage has run: int vboot_check_recovery_request(void) int vboot_recovery_mode_enabled(void) int vboot_developer_mode_enabled(void) BUG=b:124141368, b:35576380 TEST=make clean && make test-abuild BRANCH=none Change-Id: I52d17a3c6730be5c04c3c0ae020368d11db6ca3c Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38780 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-04soc/amd: unify SMBus supportAaron Durbin
The SMBus support is identical between stoneyridge and picasso. Unify on common support code. Change-Id: Ic3412c5ee67977a45c50b68f36acc45c3d560db5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-01-31soc/amd/picasso: move to using smbus_host.h definitionsAaron Durbin
The SMBus function declarations were duplicated. Use the common ones provided by smbus_host.h. Change-Id: Ia8fec8f58d72690d73f2241e69b3ff05f74943a4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38615 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-31soc/amd/picasso: use SMBus timeout in compilation unitAaron Durbin
The timeout is fixed and only used in one place. Put the assumption in the compliation unit utilizing the defintion. Change-Id: I93c061e74df6b4265fd1c61fc4669410ebc9554f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-31soc/amd/picasso: use SMBus speed in compilation unitAaron Durbin
The fixed bus speed of 400 kHz doesn't need to reside in a header file. Just move the assumption into the code itself. Change-Id: I8bb68607070d0daeae2ad3bcd79f49d5c20048fd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-31soc/amd/stoneyridge: move to using smbus_host.h definitionsAaron Durbin
The SMBus function declarations were duplicated. Use the common ones provided by smbus_host.h. Change-Id: Ic912b91daf79ecd2c276a383edcda563891cf643 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38222 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-31soc/amd/stoneyridge: use SMBus timeout in compilation unitAaron Durbin
The timeout is fixed and only used in one place. Put the assumption in the compliation unit utilizing the defintion. Change-Id: I7537549da90d0bc158e638c533e8e8b0f1e28a7d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38612 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-31soc/amd/stoneyridge: use SMBus speed in compilation unitAaron Durbin
The fixed bus speed of 400 kHz doesn't need to reside in a header file. Just move the assumption into the code itself. Change-Id: I426fe078909a9b725c1747380d69af31292b6d1e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38611 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-29amdblocks/biosram: Do small reformattingMarshall Dawson
Remove two blank lines and reorder functions by read/write sizes. Change-Id: I7bd6ed44546d49b65135a98e424a5669d90f2867 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38146 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-22{soc,southbridge}/*/*/acpi: Add possibility to disable S4Wim Vervoorn
Some boards don't support S3 or S4. The S4 state can't be removed from the available sleep states. Add a config item that allows removal of the S4 state from the list of available sleep states. The S4 state can be removed by selecting the item on board level. For the AMD chipsets the SSFG mask is updated to remove the S4 state. BUG=N/A TEST=build Change-Id: Id802c4cc40308ddf39e99e7f226d55e0e020f0c9 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38431 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-20soc/amd/picasso: Add SMMSTORE supportMarshall Dawson
Add SMMSTORE support for saving EFI NVRAM variables in conjuction with Tianocore payload. Test: none, as this duplicates tested functionality in amd/stoneyridge. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Id05b33edf949611c3f9eac94e7b63a4266c6c4d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-01-20soc/amd/stoneyridge: Add SMMSTORE supportMatt DeVillier
Add SMMSTORE support for saving EFI NVRAM variables in conjunction with Tianocore payload. Test: build/boot several google/kahlee variants, test manipulation and persistence of Tianocore bootorder variables. Change-Id: Ida604a44d1fa5288e96dbe05de1f847e597cc95d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-03soc/amd/common/block/spi: remove code duplicationAaron Durbin
This removes all the duplicated code and logic and leverages the existing ones in libraries themselves. The current side effect is that protection cannot be fully enabled because the read, write, and write enable command are not exposed in struct spi_flash currently. That support can be revised if protection scheme makes sense for our use-cases once it's better understood. BUG=b:146928174 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I8faf9cc719ee33dd9f03fb74b579b02bbc6a5e2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/37957 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-03amdblocks/acpimmio: add missing MMIO functionsMichał Żygowski
Add missing Power Management 2, old and new GPIO functions to modify the contents of these MMIO blocks. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ie4db6a4d12d9122ea5b87147adbf7b632ac2b311 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-01-03amdblocks/biosram: Force use of abstractionKyösti Mälkki
Hide the fundamental BIOSRAM accessors to force use of the memory space via abstraction functions. Change-Id: I774b6640cdd9873f52e446c4ca41b7c537a87883 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37862 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-28 09:42:15 +0000