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2020-09-14soc/amd/picasso: Move sd_emmc_config into emmc_config structRaul E Rangel
I plan on adding another eMMC parameter. This refactor keeps the config contained in a single struct. BUG=b:159823235 TEST=Build test Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4b57d651ab44d6c1cad661d620bffd4207dfebd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-09-14soc/amd/picasso: copy local info to transfer bufKangheui Won
We added transfer_info_struct to contain various information about memory region we pass from PSP to x86 in commit 0c12abe462. This should be at the start of transfer region but we only manipulated it as local variable and didn't put data into the region, resulting garbage data for transfer_info when x86 tries to read it. Copy the content of local variable to beginning of _transfer_buffer before requesting transfer to PSP so coreboot on x86 can access it. BUG=b:159220781 BRANCH=zork TEST=check transfer_info_struct is correctly populated on romstage Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I14bc34e6af501240a6f633db3999a7759e88d60b Reviewed-on: https://review.coreboot.org/c/coreboot/+/44751 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-13soc/amd/picasso/chip: fix typo in acp_pme_enableFelix Held
That devicetree setting is about the Audio Co-Processor and not ACPI. BRANCH=zork Change-Id: I7f376371ee094392d4434340c77f0fc8d0d8e4e1 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-09-13soc/amd/picasso/aoac: make AOAC device number unsignedFelix Held
The AOAC device number is never negative, so make it unsigned. BRANCH=zork Change-Id: I3e0d15a646f02da5767504471961d5d9f8f28bea Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45308 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-13soc/amd/picasso/uart: make AOAC device ID in uart_enable unsignedFelix Held
This change is separate from CB:45308 to only have the directly UART- related changes in this patch train. BRANCH=zork Change-Id: Ie587fdbd1e6229c1374fce3568c6a361577dc6c4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-13soc/amd/picasso/uart: add missing types.h includeFelix Held
BRANCH=zork Change-Id: I51923d72a2ad8dceeef11e15fb6765262dd514d9 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-12include/console/uart: make index parameter unsignedFelix Held
The UART index is never negative, so make it unsigned and drop the checks for the index to be non-negative. Change-Id: I64bd60bd2a3b82552cb3ac6524792b9ac6c09a94 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-12soc/amd/picasso/uart: make index parameters unsignedFelix Held
The UART index is never negative, so make it unsigned and drop the check for the index to be non-negative. BRANCH=zork Change-Id: I38b5dad87f8af4fbe8ee1d919230efe48f68686c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-11soc/amd/picasso: Fix TSC frequency calculationNikolai Vyssotski
Fix TSC frequency calculation per Picasso PPR. This code was copied from Stoney and was incorrect for Picasso. BUG=b:163423984 TEST=verify Dalboz TSC to be 1GHz BRANCH=zork Change-Id: Ibe3f49c7d295e7336ee042da2b94823171b6eb55 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-09-11soc/amd/common/espi_util: clarify espi_open_io_windowFelix Held
Calling espi_open_generic_io_window in espi_open_io_window depends on the condition in the preceding if statement, so move the command into an else block to make it more obvious that this is the case. TEST=Timeless build results in identical image. Change-Id: I3039817afd79c30a2df2f2f54e7848f52dc2c487 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-09-10soc/amd/picasso: Move APCB generation out of picassoRob Barnes
Move APCB generation out of the picasso makefile and into the mainboard makefile. APCB generation tends to be mainboard specific and does not belong in the soc makefile. BUG=b:168099242 TEST=Build mandolin and check for APCB in coreboot binary Build and boot ezkinil Change-Id: Ib85ad94e515f2ffad58aafe06c1f1d4043e9303c Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45222 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10soc/amd/picasso: Add MADT entry for GNB IOAPICJason Glenesk
Add the missing entry using new Kconfig symbol for IOAPIC ID. coreboot will always enable the GNB IOAPIC. Cq-Depend: chrome-internal:3247431, chrome-internal:3253044 BUG=b:167421913, b:166519072 TEST=Boot fully to morphius board with and without amd_iommu kernel parameter. Dump MADT and IVRS tables. Cross check ioapic entries in MADT against IVRS. BRANCH=Zork Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Change-Id: Ic4a2e9b71dba948e8a4907e5f97131426d8a4a3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/45056 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10soc/amd/picasso: Assign IOAPIC IDs, GNB APIC base with FSPMarshall Dawson
Add Kconfig symbols for the FCH and GNB IOAPIC IDs, then pass the info to FSP to keep it in sync with coreboot. Do the same for the northbridge's IOAPIC base address. Use the new values where needed, and reserve the resources consumed by the GNB IOAPIC. BUG=b:167421913, b:166519072 TEST=Boot Morphius and verify settings BRANCH=Zork Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I57d3d6b2ebd8b5d511dbcb4324ea065cc3111a2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/45115 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-03soc/amd/picasso/acpi: Remove padding in IVRS table caused by realignment.Jason Glenesk
Previous CL (1916f8969b10e27fe06b3e0eb1caae632bd947f6) misinterpreted spec as requiring size alignment on all IVHD device entries. The correct requirement specifies only for 4-byte entries. The unneeded realignments result in gaps in the table. The kernel hangs in early boot due to the malformed table. Remove 8-byte entry alignment. BUG=b:166519072 TEST=Boot fully to morphius board with and without amd_iommu kernel parameter. Confirm IVRS contains no alignment gaps/corruption. Change-Id: Iddcff98279be1d910936b13391dd2448a3bb2d74 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-09-03soc/amd/picasso: Set max_speed_mts and configured_speed_mtsRob Barnes
ddr_frequency is deprecated. Set max_speed_mts and configured_speed_mts instead. This will result in SMBIOS type 17 displaying more accurate speed information. BUG=b:167218112 TEST=Boot ezkinil and observe dmidecode -t17 dmidecode -t17 # dmidecode 3.2 Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x000B, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 4096 MB Form Factor: SODIMM Set: None Locator: Channel-0-DIMM-0 Bank Locator: BANK 0 Type: DDR4 Type Detail: Synchronous Speed: 3200 MT/s Manufacturer: Unknown (0) Serial Number: 00000000 Asset Tag: Not Specified Part Number: MT40A512M16TB-062E:J Rank: 1 Configured Memory Speed: 2400 MT/s Minimum Voltage: Unknown Maximum Voltage: Unknown Configured Voltage: Unknown Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I1879676ea9436b6d19c768f1b78487a4e179f8d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44984 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-03soc/amd/picasso: Only build PSP bootloader & verstage into ROMartin Roth
The PSP bootloader and verstage are only used out of the RO region, so don't build them into the RW sections. BUG=None TEST=Build & Boot BRANCH=zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ic7bcb9a6a78926325e80755c010bb047e4a9485c Reviewed-on: https://review.coreboot.org/c/coreboot/+/44990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Eric Peers <epeers@google.com>
2020-09-03soc/amd/picasso: Add config for PSP verstage signing tokenMartin Roth
This allows a platform to specify the location of the signing token for the PSP verstage, and build it into the firmware image. BUG=b:166108929 TEST=Build file into PSP firmware, verify that it's present and has the correct ID. BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I182ad9b48a2776ccd29ead0f54cfe14c5bf45560 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Eric Peers <epeers@google.com>
2020-09-03soc/amd/picasso: Allow use of pre-built PSP verstageMartin Roth
To use a signed PSP verstage, we're going to need to build it first, then sign and store the binary. This patch allows the stored (signed) verstage binary to be used. BUG=b:166108929 TEST=Build with existing verstage binary instead of re-building it. BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I5cbceca3b75f05c5460190b1c829d1ffaab2c736 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Eric Peers <epeers@google.com>
2020-09-03soc/amd/picasso: Move DRAM end to after transfer bufferJosie Nordrum
Move PSP_SHAREDMEM_DRAM_END after _etransfer_buffer to ensure that the transfer buffer actually lives within the 32KiB that is supported to be transferred. Resulting symbol address change in bootblock.debug file summarized below. BEFORE: 02011000 T _psp_sharedmem_dram 02011000 T _transfer_buffer 02011000 T _transfer_info 02011040 T _etransfer_info 02011040 T _vboot2_work 02014040 T _evboot2_work 02019000 T _epsp_sharedmem_dram 02019000 T _preram_cbmem_console 0201a600 T _epreram_cbmem_console 0201a600 T _timestamp 0201a800 T _etimestamp 0201a800 T _fmap_cache 0201ac52 T _efmap_cache 0201ac52 T _etransfer_buffer AFTER: 02011000 T _psp_sharedmem_dram 02011000 T _transfer_buffer 02011000 T _transfer_info 02011040 T _etransfer_info 02011040 T _vboot2_work 02014040 T _evboot2_work 02014040 T _preram_cbmem_console 02015640 T _epreram_cbmem_console 02015640 T _timestamp 02015840 T _etimestamp 02015840 T _fmap_cache 02015c92 T _efmap_cache 02015c92 T _etransfer_buffer 02019000 T _epsp_sharedmem_dram BUG=b:167243965 BRANCH=None TEST=checked 'cbmem -1' for FMAP error after ec reboot Signed-off-by: Josie Nordrum <josienordrum@google.com> Change-Id: I9b482aced5deb40bd87d19d9c42585d8a6db5fc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45045 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31soc/amd/picasso/southbridge: make GPP clock outputs configurableFelix Held
Make the general purpose PCIe clock outputs configurable to be either permanently enabled, permanently disabled or dynamically enabled via their corresponding external #CLK_REQx pins in the board's devicetree. BUG=b:149970243 BRANCH=zork Change-Id: I3f5760c0b869e8a9416ba9b57d182a88a2eb5e44 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-31soc/amd/picasso/southbridge.h: rename GPP clock setting offsetsFelix Held
The _SHIFT postfix is a bit clearer than the _SHL one and more in line with the names used for this kind of defines in coreboot. The documentation on that register is currently wrong and will hopefully be fixed in the future; the defines should now match the hardware. BUG=b:149970243 BRANCH=zork Change-Id: I977f107d466521484ca13fa1f4dd86a50c8150d7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-31soc/amd/picasso/southbridge.h: replace GPP_CLK_REQ_MAP_* with macrosFelix Held
Replacing the existing defines with macros makes them easier to use in a function that applies the setting for a certain GPP/GFX clock output. Also add macros for statically enabling or disabling the clock outputs and not only for configuring them as controlled by the #CLK_REQx pins. BUG=b:149970243 BRANCH=zork Change-Id: I14198f224639721fe6ca71ca3dcd9cb413a587d5 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-31soc/amd/picasso/southbridge.h: remove OSCOUT*_CLK_OUTPUT_ENB definitionsFelix Held
On Picasso MISC_CLK_CNTL1 doesn't contain OSCOUT[12]_CLK_OUTPUT_ENB and this was probably just copied over from stoneyridge. BUG=b:149970243 BRANCH=zork Change-Id: I32f459026c4e8632672123681b20736245f198b2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44886 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28amd/picasso/psp_verstage: add vboot rsa functionKangheui Won
Add vb2ex_hwcrypto_rsa_verify_digest function for verifying rsa signature against digest using PSP svc. This function will be later used by vboot to accelerate rsa verification. BUG=b:163710320, b:161205813 TEST=build zork firmware with vboot modification, confirm it's booting and boot time is reduced by ~230ms. Change-Id: Ic5c1d13092db5a84191642444f3df9c26925e475 Signed-off-by: Kangheui Won <khwon@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44456 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28soc/amd/picasso/romstage: Set SATA enable UPD if controller is enabledMatt Papageorge
FSP has recently added support for a UPD switch to power gate SATA. This change adds the coreboot side of the feature. To avoid having two SATA enable options, the value of the sata_enable UPD is determined by the enable state of the AHCI controller in the platform devicetree. BUG=b:162302027 BRANCH=zork TEST=Verify AHCI controller can be hidden/disabled. Change-Id: I48bf94a7e6249db6079a6e3de7456a536d54a242 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44067 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28mb/google/zork: Switch zork to use spd_toolsRob Barnes
Switch all zork boards to use generated generic SPDs from spd_tools. HMAA1GS6CMR6N-VK is unused by Ezkinil, and all other boards, so it was removed. picasso/Makefile.inc was updated to populate the 2nd APCB channel based on APCB_POPULATE_2ND_CHANNEL. This removes the need to suffix spd entires with _x1/_x2. Command to generate files: $ find src/mainboard/google/zork/variants/ -maxdepth 1 -type d | grep -v '/$' | while read b; do n=$(basename ${b}); if [ "${n}" = "baseboard" ]; then continue fi go run util/spd_tools/ddr4/gen_part_id.go src/mainboard/google/zork/spd \ src/mainboard/google/zork/variants/${n}/spd \ src/mainboard/google/zork/variants/${n}/spd/mem_parts_used.txt done BUG=b:162939176 TEST=Boot ezkinil and dalboz check dmidecod -t17 Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I0553858f83d3d1e90cf35bece108768f004a29a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44480 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-25soc/amd/picasso: If psp_verstage is in RO, don't reset on errorMartin Roth
If there's already been an error and PSP_verstage is booting to RO, don't reset the system. It may be that the error is fatal, but if the system is stuck, don't intentionally force it into a reboot loop. BUG=None TEST=Force an error, still boots to RO instead of going into a boot loop Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ibb6794fefe9d482850ca31b1d3b0d145fcd8bb8f Reviewed-on: https://review.coreboot.org/c/coreboot/+/44652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-24soc/amd/picasso: Reboot for recovery if no psp workbuf is foundMartin Roth
Instead of halting if the vboot workbuf is not passed to coreboot by the PSP, reset and reboot into recovery mode. This process is made more difficult because if the workbuf isn't available, we can't reboot directly into recovery - the workbuf is needed for that process to be done through the regular calls, and we don't want to go around the vboot API and just write into VBNV directly. To overcome this, we set a CMOS flag, and reset the system. PSP_verstage checks for this flag so it will update VBNV and reset the system after generating the workbuf. BUG=b:152638343 TEST=Simulate the workbuf not being present and verify the reboot process. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I049db956a5209904b274747be28ff226ce542316 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-24mrc_cache: Add mrc_cache fetch functions to support non-x86 platformsShelley Chen
Create two new functions to fetch mrc_cache data (replacing mrc_cache_get_current): - mrc_cache_load_current: fetches the mrc_cache data and drops it into the given buffer. This is useful for ARM platforms where the mmap operation is very expensive. - mrc_cache_mmap_leak: fetch the mrc_cache data and puts it into a given buffer. This is useful for platforms where the mmap operation is a no-op (like x86 platforms). As the name mentions, we are not freeing the memory that we allocated with the mmap, so it is the caller's responsibility to do so. Additionally, we are replacing mrc_cache_latest with mrc_cache_get_latest_slot_info, which does not check the validity of the data when retrieving the current mrc_cache slot. This allows the caller some flexibility in deciding where they want the mrc_cache data stored (either in an mmaped region or at a given address). BUG=b:150502246 BRANCH=None TEST=Testing on a nami (x86) device: reboot from ec console. Make sure memory training happens. reboot from ec console. Make sure that we don't do training again. Signed-off-by: Shelley Chen <shchen@google.com> Change-Id: I259dd4f550719d821bbafa2d445cbae6ea22e988 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44006 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24soc/amd/common: Move interrupt and wake status clearJosie Nordrum
Move interrupt status and wake status clearing to after GPIO config so that configuration does not incorrectly set interrupt or wake status. i.e. when PULL_UP is configured on a pad, it incorrectly sets in the interrupt status bit. Thus, the interrupt status bit must be cleared after initial pad configuration is complete. BUG=b:164892883, b:165342107 TEST=None BRANCH=None Signed-off-by: Josie Nordrum <josienordrum@google.com> Change-Id: If4a5db4bfa6a2ee9827f38e9595f487a4dcfac2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/44640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-24soc/amd/picasso: Add console & timestamp buffers to psp_verstageMartin Roth
Create areas for console & timestamp data in psp_verstage and pass it to the x86 to save for use later. BUG=b:159220781 TEST=Build & Boot trembyle Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I41c8d7a1565e761187e941d7d6021805a9744d06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-08-24soc/amd/picasso: Store ddr_frequency in MT/sRob Barnes
This field eventually gets interpreted as MT/s by SMBIOS instead of MHz. Translate from Mhz to MT/s by multiplying by 2. BUG=b:154654737 TEST=dmidecode -t 17 matches expected speed Change-Id: I51b58cb0380f2a2bf000347395ac918ac0717060 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-23soc/amd/picasso/romstage: Set HDA disable UPD if controller disabledFelix Held
FSP has recently added support for a UPD switch to disable the non-GPU HD Audio controller. This change adds the coreboot side of the feature. To avoid having two HD Audio enable options, the value of the hd_audio_enable UPD is determined by the enable state of the non-GPU HD Audio controller in the platform devicetree. BUG=b:158535201,b:162302028 BRANCH=zork TEST=With the corresponding FSP change applied the non-GPU HD Audio device is hidden when switched off in devicetree and remains present and functional when switched on in devicetree. Change-Id: Ib2965e0742f4148e42a44ddad8ee05f0c4c7237e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44680 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-21soc/amd/picasso: If using VBOOT, skip the APOB_NV region for ROMartin Roth
When booting from the RO region of a VBOOT enabled ROM, there shouldn't be a reliance on anything outside of the RO section. This includes the APOB_NV region (similar to the MRC cache region). By skipping the region when setting up the BIOS Directory table, the PSP won't try to use the region when booting. The APOB_NV region is still used for the VBOOT RW sections. BUG=b:158363448 TEST=Build RO with no APOB_NV region. Dump the BDT and verify that it's not in RO, but is in RW_A & RW_B. Boot into recovery. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I13c35ba8a2331492744d2acf257db15e4a53102a Reviewed-on: https://review.coreboot.org/c/coreboot/+/44046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-21soc/amd/common: add rudimentary ATIF supportAaron Durbin
The Linux kenerl driver for AMD gpu currently has a floor value of 12 for brightness settings (AMDGPU_DM_DEFAULT_MIN_BACKLIGHT). AMD indicates they did this because they were concerned with certain panels flickering at lower backlight values. However, for unaffected panels it's desirable to be able to have the panel "turn off" at the lowest backlight setting. The only way to do that is to provide ATIF bindings that indicate backlight range. Option SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF is added to provide a full range for the backlight setting. If needed, this path can be built upon for fuller support, but for the time being this is the only thing necessary to make the backlight be full range. BUG=b:163583825 Change-Id: If76801a8daf6a5e56ba7d118956f3ebce74e567a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-20soc/amd/acpi: Move ACPI IVRS generation to corebootJason Glenesk
Add code for IVRS generation to coreboot. Publish coreboot generated structure rather than IVRS generated by FSP binary. Reference Doc: 48882_IOMMU_3.05_PUB.pdf BUG=b:155307433 TEST=Boot trembyle to shell and extract and compare IVRS tables and make sure they cover the same devices. Change-Id: I693f4399766c71c3ad53539634c65ba59afd0fe1 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-08-19soc/amd/picasso: log and print GPIO wake eventsAaron Durbin
Capture the GPIO subsystem wake state and add events to the eventlog. BUG=b:159947207 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I7f10bf4599ea7928cc87b6b10ac11a7c30e58406 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-19soc/amd/common: add gpio subsystem event reportingAaron Durbin
In order to log gpio events for wake purposes the state of the gpio subsystem should be snapshotted. Add the ability to capture state of gpio subystem as well as saving up to 16 gpios that indicate their wake status. Likewise, provide the eventlog additions based on state. BUG=b:159947207 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I49fca56c87543aa8aad0eb7da5c5cb570c4349d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44534 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-19soc/amd/picasso: Use cbfs to locate the AMD firmwareMartin Roth
Switch from locating the AMD firmware in the RW_A & RW_B regions with their hardcoded locations to using CBFS to find them. They still need to be at the hardcoded locations so that we can set the location inside the binary, but instead of just setting the pointer directly to them, we now search for them with cbfs. BUG=b:154441227 TEST=Boot & verify that binaries are located in both RW-A & RW-B Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I27b0593e0db7a9e6ba9b0633ac93b4d93954f002 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42831 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-19soc/amd/picasso: Remove now unused #defineMartin Roth
This #define wasn't removed when the tests were removed, so get rid of it now. BUG=None TEST=Build Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ie0005b6ee97037bf3dfb80f0c2408d8bd9ee9633 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-08-18soc/amd/picasso: fix GPE snapshot stateAaron Durbin
In CB:44488 the cbmem addition was re-filling the object when it should be memcpy()ing from static object. Correct that oversight. The side effect from the previous implementation would be if FSP-M modified the GPE state. BUG=b:159947207 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I158a89ae28431896fa9b5789292000fcbf0b066d Reviewed-on: https://review.coreboot.org/c/coreboot/+/44533 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-18elog: rename ELOG_WAKE_SOURCE_GPIO to ELOG_WAKE_SOURCE_GPEAaron Durbin
The wake source macro for GPE events was using 'GPIO'. However, current usage is really all GPEs. Therefore, provide clarity in the naming in order to allow for proper GPIO wake events that are separate from the ACPI GPE block. BUG=b:159947207 Change-Id: I27d0ab439c58b1658ed39158eddb1213c24d328f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-18src: Remove unused 'include <delay.h>'Elyes HAOUAS
Change-Id: I6afea5c102299e570378a1656d3dcd329a373399 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44093 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-18src: Remove unuse '<timestamp.h>Elyes HAOUAS
Change-Id: I4fa03c4576bb0256b73f1d36ca840e120b750a74 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-08-18src: Remove unneded whitespace before tabElyes HAOUAS
Also remove unneded tab in 'picasso/Makefile.c' file. Change-Id: Id25b2d308645c449c205b3a946f89b6b6de62a47 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-08-17soc/amd/common: add GPE event logsAaron Durbin
GPE events were not be recorded in the eventlog. Add those to the eventlog when the status register indicates those events. BUG=b:159947207 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ifb3167fd24f2171b2baf1a65eb81a318eb3e7a86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-17soc/amd/picasso: snapshot chipset state early in boot sequenceAaron Durbin
Previously the chipset state was snapshotted very late in the boot (ramstage). Instead start gathering the state early in romstage prior to calling any FSP routines so there's a clean snapshot. BUG=b:159947207 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Id41686e6cdf5bebc9633b514b4121b0447f9be2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/44488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-17soc/amd/stoneyridge: remove unused soc_power_reg objectAaron Durbin
Now that no one is consuming this object, remove its definition. BUG=b:159947207 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ib5aeec1733b6c9fa49569e30c4c369f70af0939c Reviewed-on: https://review.coreboot.org/c/coreboot/+/44487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-17soc/amd/picasso: remove unused soc_power_reg objectAaron Durbin
Now that no one is consuming this object, remove its definition. BUG=b:159947207 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I60e4a9bfdf2752923f46a35aaab7034f9fa9b309 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-17soc/amd/common: removed unused functionsAaron Durbin
Now that all users of the functions manipulating global state and using soc-specific objects are removed remove those functions. BUG=b:159947207 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I18c4c8b0c7852dde8cf0b6b3f11e43e15c3ce155 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 08:43:50 +0000