summaryrefslogtreecommitdiff
path: root/src/soc/imgtec/pistachio/ddr2_init.c
AgeCommit message (Expand)Author
2015-12-21imgtec/pistachio: DDR2, DDR3: DLL reset setIonela Voinescu
2015-12-21imgtec/pistachio: DDR2, DDR3: DQS gate earlyIonela Voinescu
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-06-12pistachio: add DDR3 initialization codeIonela Voinescu
2015-06-12pistachio: Use passive windowing as DQS gating schemeIonela Voinescu
2015-06-10pistachio: sort included header filesIonela Voinescu
2015-05-21Remove address from GPLv2 headersPatrick Georgi
2015-04-22imgtec/pistachio: DDR reads return to controller with no bubblesIonela Voinescu
2015-04-22imgtec/pistachio: DDR row/bank/column mappingIonela Voinescu
2015-04-21pistachio: Remove 50% DDR bandwidth restrictionIonela Voinescu
2015-04-21pistachio: Decrease DDR ODT from 75R to 50RIonela Voinescu
2015-04-21pistachio: clean DDR2 initialization codeIonela Voinescu
2015-04-17pistachio: add DDR2 initialization codeIonela Voinescu