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coreboot
2560p
820g2
autoport-hsw
broadwell_refcode
e6230
e7240_bdw
haswell-mrc
hp820g1
hp9480m
mec1322
Some coreboot project code with my work
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imgtec
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pistachio
Age
Commit message (
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Author
2015-04-14
pistachio: Use 1.8433179 MHz for UART refclk
David Hendricks
2015-04-14
pistachio: increase size of bootblock to 18 KB
Ionela Voinescu
2015-04-14
pistachio: change memory layout as to allow bigger CBFS cache
Ionela Voinescu
2015-04-14
pistachio: spi: use same clock edge for RX and TX
Ionela Voinescu
2015-04-14
urara: Configure clocks and MFIOs
Ionela Voinescu
2015-04-14
CBFS: Automate ROM image layout and remove hardcoded offsets
Julius Werner
2015-04-13
spi: support controllers with limited transfer size capabilities
Vadim Bendebury
2015-04-13
urara: add support for DMA coherent memory area
Ionela Voinescu
2015-04-13
pistachio: increase the size of romstage to 36K
Ionela Voinescu
2015-04-09
pistachio: add timer frequency for SOC; correct platform ID
Ionela Voinescu
2015-04-09
pistachio: add SOC descriptor
Vadim Bendebury
2015-04-09
pistachio: modify memory layout
Vadim Bendebury
2015-04-09
pistachio: set correct CBMEM top address
Vadim Bendebury
2015-04-09
pistachio: allow more room for bootblock
Vadim Bendebury
2015-04-09
pistachio: implement timer support
Vadim Bendebury
2015-04-07
pistachio: Change all SoC headers to <soc/headername.h> system
Julius Werner
2015-04-06
New mechanism to define SRAM/memory map with automatic bounds checking
Julius Werner
2015-04-02
pistachio: add gpio type definition
Vadim Bendebury
2015-04-02
urara: Fix CBFS header definitions
Vadim Bendebury
2015-03-30
imgtec/pistachio: Bring uart driver to modern standards
Patrick Georgi
2015-03-28
pistachio: don't open code ramstage loading
Aaron Durbin
2015-03-27
soc/imgtec/pistachio: Add IMGTEC SPI controller driver
Ionela Voinescu
2015-03-27
urara: use proper SOC name
Vadim Bendebury