summaryrefslogtreecommitdiff
path: root/src/soc/imgtec/pistachio
AgeCommit message (Expand)Author
2015-09-22linking: link bootblock.elf with .data and .bss sections againAaron Durbin
2015-09-09verstage: use common program.ld for linkingAaron Durbin
2015-08-31imgtec/pistachio: remove timestamp_get() implementationAaron Durbin
2015-08-09imgtech/pistacho: Add vboot2 memory regionPatrick Georgi
2015-06-24Remove address from GPLv2 headersPatrick Georgi
2015-06-21Remove old HAVE_UART_MEMORY_MAPPED select statementsMartin Roth
2015-06-12pistachio: add DDR3 initialization codeIonela Voinescu
2015-06-12pistachio: Use passive windowing as DQS gating schemeIonela Voinescu
2015-06-10pistachio: sort included header filesIonela Voinescu
2015-06-10pistachio: initialize cbmem area to be emptyIonela Voinescu
2015-06-09pistachio: increase romstage sizeIonela Voinescu
2015-06-02Revert "pistashio: bump up romstage size"Aaron Durbin
2015-05-26pistashio: bump up romstage sizeAaron Durbin
2015-05-21Remove address from GPLv2 headersPatrick Georgi
2015-05-19Remove Kconfig variable that has no effectPatrick Georgi
2015-05-07imgtec/pistachio: Add comment on the unusual memory layoutPatrick Georgi
2015-04-30imgtech/pistachio: Give some more space to the bootblockPatrick Georgi
2015-04-29kbuild: automatically include SOCsStefan Reinauer
2015-04-22imgtec/pistachio: DDR reads return to controller with no bubblesIonela Voinescu
2015-04-22imgtec/pistachio: DDR row/bank/column mappingIonela Voinescu
2015-04-22soc: select generic gpio lib on (almost) all non-x86 SOCsStefan Reinauer
2015-04-22imgtec/pistachio: increase RAM CBFS cache sizeVadim Bendebury
2015-04-21pistachio: Remove 50% DDR bandwidth restrictionIonela Voinescu
2015-04-21pistachio: Decrease DDR ODT from 75R to 50RIonela Voinescu
2015-04-21pistachio: clean DDR2 initialization codeIonela Voinescu
2015-04-21pistachio: add clock setup for all I2C interfacesIonela Voinescu
2015-04-21urara: Identity map DRAM/SRAMAndrew Bresticker
2015-04-21imgtec/pistachio: Add spi_crop_chunk()Patrick Georgi
2015-04-17pistachio: Move console UART to a Kconfig variableDavid Hendricks
2015-04-17pistachio: add DDR2 initialization codeIonela Voinescu
2015-04-17pistachio: report UART register widthVadim Bendebury
2015-04-17uart: pass register width in the coreboot tableVadim Bendebury
2015-04-14pistachio: implement clock setup for I2C0Ionela Voinescu
2015-04-14pistachio: Fix ROM clock base addressIonela Voinescu
2015-04-14urara: add clock setup for MIPS CPU, ROM and EthernetIonela Voinescu
2015-04-14pistachio: fix clocks setup codeIonela Voinescu
2015-04-14pistachio: Use 1.8433179 MHz for UART refclkDavid Hendricks
2015-04-14pistachio: increase size of bootblock to 18 KBIonela Voinescu
2015-04-14pistachio: change memory layout as to allow bigger CBFS cacheIonela Voinescu
2015-04-14pistachio: spi: use same clock edge for RX and TXIonela Voinescu
2015-04-14urara: Configure clocks and MFIOsIonela Voinescu
2015-04-14CBFS: Automate ROM image layout and remove hardcoded offsetsJulius Werner
2015-04-13spi: support controllers with limited transfer size capabilitiesVadim Bendebury
2015-04-13urara: add support for DMA coherent memory areaIonela Voinescu
2015-04-13pistachio: increase the size of romstage to 36KIonela Voinescu
2015-04-09pistachio: add timer frequency for SOC; correct platform IDIonela Voinescu
2015-04-09pistachio: add SOC descriptorVadim Bendebury
2015-04-09pistachio: modify memory layoutVadim Bendebury
2015-04-09pistachio: set correct CBMEM top addressVadim Bendebury
2015-04-09pistachio: allow more room for bootblockVadim Bendebury
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-23 23:26:44 +0000