| Age | Commit message (Expand) | Author |
|---|---|---|
| 2021-05-07 | soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster | Kane Chen |
| 2020-10-03 | soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage | Subrata Banik |
 |
index : coreboot | |
| Some coreboot project code with my work | vimacs |
| summaryrefslogtreecommitdiff |