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2018-10-08src: Use tabs for indentationElyes HAOUAS
Change-Id: I6b40aaf5af5d114bbb0cd227dfd50b0ee19eebba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28934 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-05src: Fix MSR_PKG_CST_CONFIG_CONTROL register nameElyes HAOUAS
Change-Id: I492224b6900b9658d54c8cf486ef5d64b299687f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2018-09-14soc/intel/denverton_ns: Enable common block PMCJulien Viard de Galbert
Mainly update headers to build. Added option PMC_GLOBAL_RESET_ENABLE_LOCK to remove function configuring the global reset through PMC base. On denverton the global reset lock is not in PMC base but in the PCI registers so this code cannot be shared. Change-Id: I9ace70862cab63f8355252d034292596c7eab1fd Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/25426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Evandro Luiz Hauenstein <kingsumos@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-13src/*/intel/: clarify Kconfig options regarding IFDStefan Tauner
HAVE_INTEL_FIRMWARE is used to enable certain options that rely on a valid Inter Flash Descriptor to exist. It does *not* identify platforms or boards that are capable of running in descriptor mode if it's valid. Refine the help text to make this clear. Introduce a new option INTEL_DESCRIPTOR_MODE_CAPABLE that does simply declare that IFD is supported by the platform. Select this value everywhere instead of the HAVE_INTEL_FIRMWARE and default HAVE_INTEL_FIRMWARE to y if INTEL_DESCRIPTOR_MODE_CAPABLE is selected. Move the QEMU Q35 special case (deselection of HAVE_INTEL_FIRMWARE) to the mainboard directory. Change-Id: I4791fce03982bf0443bf0b8e26d9f4f06c6f2060 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/28371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-06chromeos/gnvs: remove function and naming cleanupJoel Kitching
- Remove unused acpi_get_chromeos_acpi_info (see CB:28190) - Make function naming in gnvs.h consistent (start with "chromeos_") BUG=b:112288216 TEST=compile and run on eve Change-Id: I5b0066bc311b0ea995fa30bca1cd9235dc9b7d1b Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/28406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-31siemens/mc_apl1: Correct the Tx signal from SATA interfaceMario Scheithauer
Because of an incorrect transmit voltage swing, the signal must be adjusted. The factor of slices for full swing level can be corrected via the High Speed I/O Transmit Control Register 3. Change-Id: I116802cd2a944658fc3022e948eba43cebe52bb4 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
2018-08-28siemens/mc_apl1: Extend circuit life by clock gating and power gatingMario Scheithauer
The firmware of devices connected to LPC should deassert the LPC CLKRUN# signal when there is no bus activity on LPC. Necessary changes: - Enable LPC CLKRUN# - Enable LPC PCE (Power Control Enable) - Enable LPC CCE (Clock Control Enable) - Remove I/O decoding range on LPC for COM 3 - Disable I/O UART driver Change-Id: I2fd80e3fdcf23658f97b8182a77df7e09ddf25d6 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-24soc/intel/apollolake: Make eMMC max speed configurableMario Scheithauer
The eMMC maximum speed is set to HS400 mode per default. To increase the lifetime of the circuit, it is necessary to reduce the eMMC speed. Change-Id: I6fa5eb56a0593e24269ef143645c506232879889 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28282 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-22soc/intel/apollolake: Fix logical vs. bitwise operatorJohn Zhao
src/soc/intel/apollolake/chip.c Apply bitwise operator instead of logical one. Found-by: Coverity Scan BRANCH=None TEST=Built & booted Yorp board. Change-Id: I36746b04dec889f53c8d7eeb3b1d8118eff1de42 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-22cbtable: remove chromeos_acpi from cbtableJoel Kitching
Since we can derive chromeos_acpi's location from that of ACPI GNVS, remove chromeos_acpi entry from cbtable and instead use acpi_gnvs + GVNS_CHROMEOS_ACPI_OFFSET. BUG=b:112288216 TEST=None CQ-DEPEND=CL:1179725 Change-Id: I74d8a9965a0ed7874ff03884e7a921fd725eace9 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/28190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-20soc/intel/common/block: Move common uart function to block/uartSubrata Banik
This patch moves uart functions which are common across multiple soc to block/uart. This will remove redundant code copy from soc {skylake/apollolake/cannonlake}. BUG=b:78109109 BRANCH=none TEST=Build and boot on KBL/APL/CNL platform. Change-Id: I109d0e5c942e499cb763bde47cb7d53dfbf5cef6 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-20soc/intel/apollolake: Force USB-C into host modeJohn Zhao
When USB OTG is set, GLK FSP enables xHCI SW ID pin and configures USB-C as device mode. Force USB-C into host mode. BUG=b:111623911 TEST=Verified that USB-C being host mode once USB OTG is set. Change-Id: Iaca3d25a1159f922b743963cbc508d8defa7b6ff Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/27746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-13intel/apollolake: Fix typo in dptf.aslChris Zhou
Fix define typo in dptf.asl BUG=none TEST=emerge-octopus coreboot PASS Change-Id: I1c3bd55d1507e6fffe638bba38c99a9851b8a96a Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-08-12soc/intel/apollolake: Get rid of cnvi.aslFurquan Shaikh
There is no need to add a special cnvi.asl file for the CNVi device. This can be handled by drivers/intel/wifi just like a PCIe WiFi device. This change gets rid of the cnvi.asl file and its usage in southbridge.asl file. BUG=b:112371978 Change-Id: I0b798cdd430768730b7ada61ca4cb1f63c2a4229 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-12soc/intel/apollolake: Add CNVi device to list of PCI devsFurquan Shaikh
This change adds CNVi device to list of PCI devs. BUG=b:112371978 Change-Id: I6def98db3846c2244812a9a2ce84340bd2149b48 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-10drivers/i2c: Add i2c TPM support for different stagesPhilipp Deppenwiese
Change-Id: Ib0839933f8b59f0c87cdda4e5374828bd6f1099f Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/23759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-08-08soc/intel/apollolake: add new dimm info saving APIAaron Durbin
The current call for saving dimm info passed the lpddr4_cfg and memory sku id. In order to prepare decoupling the part number from lpddr4_cfg provide a new API, save_lpddr4_dimm_info_part_num(), which explicitly takes the part number. The previous API now uses the new one internally. BUG=b:112203105 Change-Id: Ieadf452b6daa3231a0c5e3be61b0603b40d0fff2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/27944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-08soc/intel/apollolake: Add support for LPDDR4 nWR settingRavi Sarawadi
nWR (Write-Recovery for AutoPre-charge commands), the programmed value of nWR is the number of clock cycles the LPDDR4-SDRAM device uses to determine the starting point of an internal Pre-charge operation after a Write burst with AP (auto-pre-charge) enabled. For >2133MHz speed parts the nWR needs to be set to 24 clock cycles. The nWR field, though, is only in the GLK FSP, so just update that field conditionally based on the GLK Kconfig option. BUG=b:112062440 TEST= build test Change-Id: I1147538f72f4e2f14e32f3657c05f1f505a56fbf Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/27850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-25soc/intel/apollolake: Get rid of power button device in corebootFurquan Shaikh
As per the ACPI specification, there are two types of power button devices: 1. Fixed hardware power button 2. Generic hardware power button Fixed hardware power button is added by the OSPM if POWER_BUTTON flag is not set in FADT by the BIOS. This device has its programming model in PM1x_EVT_BLK. All ACPI compliant OSes are expected to add this power button device by default if the power button FADT flag is not set. On the other hand, generic hardware power button can be used by platforms if fixed register space cannot be used for the power button device. In order to support this, power button device object with HID PNP0C0C is expected to be added to ACPI tables. Additionally, POWER_BUTTON flag should be set to indicate the presence of control method for power button. Chrome EC mainboards implemented the generic hardware power button in a broken manner i.e. power button object with HID PNP0C0C is added to ACPI however none of the boards set POWER_BUTTON flag in FADT. This results in Linux kernel adding both fixed hardware power button as well as generic hardware power button to the list of devices present on the system. Though this is mostly harmless, it is logically incorrect and can confuse any userspace utilities scanning the ACPI devices. This change gets rid of the generic hardware power button from APL and relies completely on the fixed hardware power button. BUG=b:110913245 TEST=Verified that fixed hardware power button still works as expected on octopus. Change-Id: I86259465c6cfaf579dd7dc3560b4c9e676b80b55 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27273 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-24cpu/x86/mtrr.h: Rename MSR SMRR_PHYS_x to IA32_SMRR_PHYSxArthur Heymans
This is how these MSR's are referenced in Intel® 64 and IA-32 Architectures Software Developer’s Manual. The purpose is to differentiate with MSR_SMRR_PHYSx. Change-Id: I54875f3a6d98a28004d5bd3197923862af8f7377 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-28intel/common: change mca_configure API's defPratik Prajapati
add an unused param so that mca_configure can be called by mp_run_on_all_cpus to run it on all cores. Change-Id: I2395ee7fbedc829f040959b0021967f800693eeb Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/26391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-06-28soc/intel/common/block: Move p2sb common functions into block/p2sbSubrata Banik
This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving common soc code into common/block/p2sb. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL/CNL/APL platform. Change-Id: Ie9fd933d155b3fcd0d616b41cdf042cefe2c649a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-28soc/intel/apollolake: Remove dead filesFurquan Shaikh
Change a86d1b8 (soc/intel/common: Add SMM common code for Intel Platforms) moved APL to use common SMM code. However, smi.c and smm.h files under soc/intel/apollolake/ were not removed. This change removes the dead files since they are not used anymore. BUG=b:110836465 Change-Id: I1ff213372521fd47e2335de6a4b438d16c74ecd3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-28soc/intel/apollolake: Remove call to pmc_fixup_power_stateFurquan Shaikh
On APL, call to pmc_fixup_power_state was added because GPE0_EN registers did not have the right bits set on resume from S3 -- this was a result of GPE_CFG registers getting reset to their default state on resume. GPE_CFG registers are programmed as part of pmc_gpe_init which was previously done only in ramstage. However, with change a673d1c (soc/intel/apollolake: Initialize GPEs in bootblock), call to pmc_gpe_init was added to bootblock which means that GPE_CFG registers will have the right state by the time control reaches romstage where pmc_fill_power_state is called. Thus, call to pmc_fixup_power_state is totally redundant and in fact leads to side-effects because of the call to pmc_disable_all_gpe at the end of pmc_fill_power_state. BUG=b:110836465 TEST=Verified on yorp that wake source is correctly identified on resume from S3. Change-Id: Ia63ddbe381ce8a59736c231d745fd71d008d5d92 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-26soc/intel/apollolake: Enable logging for wake sources in S0ixFurquan Shaikh
This change adds GSMI callback elog_gsmi_cb_platform_log_wake_source to enable wake source logging from S0ix on APL/GLK. Additionally, elog.c is added to smm stage. BUG=b:79449585 TEST=Verified that S0ix entry/exit events are added to eventlog: =========== Power button ============ 59 | 2018-06-25 14:01:11 | S0ix Enter 60 | 2018-06-25 14:01:30 | S0ix Exit 61 | 2018-06-25 14:02:00 | Wake Source | Power Button | 0 =========== Lid open ================ 62 | 2018-06-25 14:02:36 | S0ix Enter 63 | 2018-06-25 14:02:56 | S0ix Exit 64 | 2018-06-25 14:03:26 | Wake Source | GPE # | 15 65 | 2018-06-25 14:03:32 | Wake Source | GPE # | 65 66 | 2018-06-25 14:03:37 | EC Event | Lid Open =========== Trackpad ================ 67 | 2018-06-25 14:04:20 | S0ix Enter 68 | 2018-06-25 14:04:33 | S0ix Exit 69 | 2018-06-25 14:05:03 | Wake Source | GPE # | 15 70 | 2018-06-25 14:05:08 | Wake Source | GPE # | 66 Change-Id: I005de58c73d00dc9d7e64f1459f6d786792b94db Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27234 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-22soc/intel/common/block/cpu: Add option to skip coreboot AP initSubrata Banik
SoC users from IOTG team is looking forward for a solution to skip coreboot AP initialization flow and make use of FSPS-UPD to perform AP reset. TEST=Assign use_fsp_mp_init=1 to ensure coreboot is not bringing APs out of reset. Change-Id: Ibc8cd411e802fb682436a933073922b2693ba994 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-21soc/intel/apollolake: unify definition for spi base addressBora Guvendik
Use SPI_BASE_ADDRESS instead of PRERAM_SPI_BASE_ADDRESS like big core in order make common code implementation straightforward. Change-Id: Ibcb013fc95de29234253e89c9ca100cc468d44f6 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/27097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-15soc/intel/{glk,apl} and mainboards: Configure LPC_CLKRUN# pin as GPIO for S0ixHannah Williams
This pin does not have a native function for eSPI. Nonetheless if we use eSPI, it should be configured as a GPIO and kept unconnected to allow S0ix entry. Also removed initialization of LPC pins in mainboard code as they are already initialized in chipset code. The settings fpr LPC pins in chipset code were updated to those that were previously in mainboard code and have been validated on LPC flavor of Geminilake RVP. BUG=b:79251613 BRANCH=none TEST=From kernel prompt in bip, type powerd_dbus_suspend. Check on EC console that SOC enters S0ix. Change-Id: Ie0c1013fee638a3b7a91469736efc0c25a1597fa Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/23742 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-14src: Get rid of device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: I6adc0429ae9ecc8f726d6167a6458d9333dc515f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14src: Use of device_t is deprecatedElyes HAOUAS
Change-Id: I9cebfc5c77187bd81094031c43ff6df094908417 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14soc/intel/{glk,apl}: ensure C1E is disabled after S3 resumeCole Nelson
C1E is disabled by the kernel driver intel_idle at boot. This does not address the S3 resume case, so we lose state and C1E is enabled after S3 resume. Disable C1E for GLK as it is for APL. This gives a coherent state before and after S3 resume. TEST='iotools rdmsr cpu 0x1fc'. Returns the same value after boot and S3 resume with bit [1] set to zero (0x20005d). Change-Id: I437cbaca75c539c2bc5cd801ab8df907e7447d10 Signed-off-by: Cole Nelson <colex.nelson@intel.com> Reviewed-on: https://review.coreboot.org/27019 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-12drivers/intel/gma: Unify VBT related Kconfig namesNico Huber
Shuffle words and drop the _DATA_FILE suffix. Change-Id: I0b0d50ea729e5580c0bc7b43f250ff387ce59cfc Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-06arch/x86: Make RELOCATABLE_RAMSTAGE the defaultKyösti Mälkki
No need to provide an option to try disable this. Also remove explicit ´select RELOCATABLE_MODULES' lines from platform Kconfigs. Change-Id: I5fb169f90331ce37b4113378405323ec856d6fee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-06soc/intel/common/block: Move i2c common functions into block/i2cSubrata Banik
This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving common soc code into common/block/i2c. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL/CNL/APL platform. Change-Id: I88f2f836eee4f80b79486dd8644d1bb3826c5af1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-06soc/intel/common/block: Move gspi common functions into block/gspiSubrata Banik
This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving common soc code into common/block/gspi. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL/CNL/APL platform. Change-Id: I877c7c48af928ca1e0399ec794d9400bc52edfcb Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-06soc/intel/common/block: Add common chip config blockSubrata Banik
Adding common chip config structure which will be used to return data to common code. When common code requires soc data, code used to fetch entire soc config structure. With this change, common code will only get the data/structure which is required by common code and not entire config. For now, adding i2c, gspi and lockdown configuration which will be used by common code. BUG=none BRANCH=b:78109109 TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check values are returned properly using common structure. Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/26189 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-06soc/intel/apollolake: Add missing entries to pmc_to_gpio_route for GLKFurquan Shaikh
This change adds missing entries in PMC to GPIO route mapping for GLK. BUG=b:77224247 Change-Id: I66cadaa23b8bd4518a199733c8fba81168e60323 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-06soc/intel/apollolake: Fix macro name for GPIO_GPE_NW group 2Furquan Shaikh
Bit 63 is part of GPIO_GPE_NW group 1 and group 2 starts from bit 64. This change corrects macro name to GPIO_GPE_NW_95_64 to reflect this. BUG=b:77224247 Change-Id: Ib94617ad102eea5084281f0dda3475e33d3a7833 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-05soc/intel/{apollolake, geminilake}: Add option to skip coreboot MP initSubrata Banik
This patch provides option for mainboard to skip coreboot MP initialization if required based on use_fsp_mp_init. Option for mainboard to skip coreboot MP initialization * 0 = Make use of coreboot MP Init * 1 = Make use of FSP MP Init Default coreboot does MP initialization for APL and GLK. Change-Id: I9253af6f28bf694782c117296766fd8564dc2b14 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-04security/tpm: Unify the coreboot TPM software stackPhilipp Deppenwiese
* Remove 2nd software stack in pc80 drivers directory. * Create TSPI interface for common usage. * Refactor TSS / TIS code base. * Add vendor tss (Cr50) directory. * Change kconfig options for TPM to TPM1. * Add user / board configuration with: * MAINBOARD_HAS_*_TPM # * BUS driver * MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2 * Add kconfig TPM user selection (e.g. pluggable TPMs) * Fix existing headers and function calls. * Fix vboot for interface usage and antirollback mode. Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/24903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-04src/soc: Get rid of whitespace before tabElyes HAOUAS
Change-Id: Ia024fb418f02d90c38b9a35ff819c607b9ac4965 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04soc/{amd,intel}: Use postcar_frame_add_romcache()Nico Huber
Change-Id: Iee816628ac3c33633f5f45798562a4ce49493a65 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-04soc/intel/apollolake: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Id6bcf98892c1944ec9c7e637f63c4c05fe9a0c07 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-03soc/intel/apollolake: Add Page table mapping for System MemoryHannah Williams
Since we do not know before hand the memory range initialized by FSP memory init until it completes and as memory gets accessed from within FSP memory init to migrate FSP from CAR to memory, we need to add this mapping in coreboot. Change-Id: I1ce2d489240e6e3686ceb7f6e824e5a94398d47e Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/26745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-31soc/{amd,intel}: Use CACHE_ROM_(BASE|SIZE)Nico Huber
Boards could choose a high ROM_SIZE that would result in an MTRR config that conflicts with other resources. Thus, always use the filtered CACHE_ROM_SIZE. Change-Id: I66d36b84ce49c1cb98cb36a4731977baaedf3225 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26575 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-22soc/intel/apollolake: Bypass FSP's CpuMemorytest, PCIe pwr seq & SPI InitSrinidhi N Kaushik
CpuMemoryTest in FSP tests 0 to 1M of the RAM after MRC init. With PAGING_IN_CACHE_AS_RAM enabled for GLK, there was no page table entry for this range which caused a page fault. Since this test is anyway not exhaustive, we will skip the memory test in FSP. There is an option to do PCIe power sequence from within FSP if provided with the GPIOs used for PERST to FSP. Since we do this from coreboot, will skip the PCIe power sequence done by FSP. FSP does not know what the clock requirements are for the device on SPI bus, hence it should not modify what coreboot has set up. Hence skipping SPI clock programming in FSP. CQ-DEPEND=CL:*627827 BUG=b:78599939, b:78599576, b:76058338 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: I4fa7a73fbb4676bb7af2416c8a33bf10ef41dd53 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/26284 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-22src: Remove non-ascii charactersMartin Roth
Change-Id: Iedb78e24a286a51830c85724af0179995ed553be Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-22bootblock: Allow more timestamps in bootblock_main_with_timestamp()Julius Werner
This patch adds more parameters to bootblock_main_with_timestamp() to give callers the opportunity to add additional timestamps that were recorded in the platform-specific initialization phase. Change-Id: Idf3a0fcf5aee88a33747afc69e055b95bd38750c Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/26339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-18soc/intel: Add support for USB ACPI code generationDuncan Laurie
To support generating USB devices in ACPI the platform needs to know how to determine a device name for each USB port, and for any root hubs that may be present. Recent Intel platforms route all ports to an XHCI controller through a root hub. This is supported by considering the root hub to be USB port type 0, the USB 2.0 ports to be type 2, and the USB 3.0 ports to be type 3. This was tested with a Kaby Lake platform by adding entries to the devicetree and checking the resulting SSDT. Change-Id: I527a63bdc64f9243fe57487363ee6d5f60be84ca Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/26174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-15soc/intel/apollolake: add rt5682 NHLT supportNaveen Manohar
Add APIs and required parameters for creating Realtek 5682 SSP endpoint in NHLT table. BUG=b:79235534 TEST=check that NHLT table defined is created properly. With the series merged & required driver support in kernel. Verify Headset Audio playback. Change-Id: Ic26a0b881f77af64ba00fd714b08c0f17c0acb3d Signed-off-by: Naveen Manohar <naveen.m@intel.com> Reviewed-on: https://review.coreboot.org/26057 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-17 06:06:06 +0000