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2019-03-01device/pci: Fix PCI accessor headersKyösti Mälkki
PCI config accessors are no longer indirectly included from <arch/io.h> use <device/pci_ops.h> instead. Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-02-18soc/intel: Add mem_rank info in SMBIOSFrancois Toguo
"mosys memory spd print all" returns incorrect memory ranks info. This patch and 2 upcomming ones (one in FSP) will address the issue. BUG=b:122329046 TEST=Boot to OS on Bobba variant of Octopus BRANCH=octopus Change-Id: I212215040e4786c258a9c604cc5c2bb62867c842 Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com> Reviewed-on: https://review.coreboot.org/c/31235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-05soc/intel/apl: Call mca_configure() on cold boots onlyNico Huber
By APL BIOS Spec, we must not do this on warm boots. The TODO comment seems stale and copied over. So the actual requirements for SGX are unknown and we add a guard for that case. Change-Id: I09b4a2fe22267d7318951aac20a3ea566403492e Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/31200 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-05intel/apollolake: Add parameter to enable VTD in devicetreeWerner Zeh
The FSP has a parameter to enable or disable the VTD feature (Intel's Virtualization Technology for Directed I/O). In current header files for FSP-S (Apollo Lake and Gemini Lake) this parameter is set to disabled per default. Therefore, if the FSP was not modified via BCT, this feature is most likely disabled on all mainboards. Add a chip parameter so that VTD can be enabled on mainboard level in devicetree and therefore this feature can be activated if needed. Change-Id: Ic0bfcf1719e1ccc678a932bf3d38c6dbce3556bc Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/31194 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-05soc/intel/apollolake: Update XHCI ports for GLK in ACPI tablesFurquan Shaikh
GLK has a dedicated USB2 port that is used specifically for CNVi BT. This requires that the ACPI tables define an additional USB 2 port which results in _ADR for USB 3 ports being different for GLK than APL. This change splits the ports in xhci.asl into APL and GLK specific ports.asl and selects the appropriate file based on CONFIG_SOC_INTEL_GLK. It also adds support for returning HS09 for GLK if ACPI name is requested for that port. BUG=b:123670712 BRANCH=octopus TEST=Verified that generated DSDT for octopus (GLK) includes HS09 and for reef (APL) does not include HS09 definition. Change-Id: I2d3d3690ec9ea1f6e35c38c3b3cbb82e961b7950 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/31172 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-31soc/intel/apollolake: Fix XHCI device name in ACPIKarthikeyan Ramasubramanian
XHCI is currently named as XHC1. This leads to namespace lookup error in the kernel when children USB ACPI devices are added under the scope of XHCI device. BUG=b:123296264 BRANCH=octopus TEST=Boot to ChromeOS; Ensure that the below error is resolved in the kernel dmesg [ 0.001000] ACPI Error: [\_SB_.PCI0.XHCI.RHUB.HS03] Namespace lookup failure, AE_NOT_FOUND (20170728/dswload-210) Change-Id: Ia4921547fee6fb51333319b9e881501a7e75ebce Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/31147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-01-30soc/intel/apollolake: Sync fsp upd structure updateJohn Zhao
FSP 2.0.9 provides UPD interface to adjust integrated filter value, usb3 LDO and pmic vdd2 voltage. Change coreboot upd structure to sync with fsp 2.0.9 release. BUG=b:123398358 CQ-DEPEND=CL:*817128 TEST=Verified yorp boots to kernel. Change-Id: I3d17dfbe58bdc5222378459723da8e9ac0573510 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/31131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-29soc/intel/apollolake: Add GLK usb2eye configuration overrideSeunghwan Kim
Now we have usb2eye configuration register in FSPUPD, so we need to add an interface to override usb2eye setting. BRANCH=octopus BUG=NONE TEST=Verified usb2eye custom setting works Change-Id: I5c500964658072eaaf59364242aa928df25d99d1 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/31060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-01-28intel/apollolake: Add IPU to disable_dev functionWerner Zeh
The SoC has an Image Processing Unit which is located on PCI 00:03.0. There is a corresponding parameter for FSP which handles enabling/disabling of this functionality (IpuEn). Add this device to the disable_dev() function of the chip so that if this device is disabled in devicetree the matching FSP parameter will be disabled as well. As this parameter is only valid for Apollo Lake, use the config switch CONFIG_SOC_INTEL_GLK to disable this code if compiled not for Apollo Lake. As this issue is regarding a missing structure member, this check needs to be done on preprocessor level and not at runtime. Test=Verified this function on mc_apl2. Change-Id: I75444bf483de32ba641f76ca50e9744fdce2e726 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/30992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-28intel/apollolake: Add fixed resources for VTd to system resourcesWerner Zeh
If the VTd feature is enabled, there will be up to two fixed resources which are set up by the FSP. Add these resources to the list of system resources so that the PCI enumerator will know them. Change-Id: If96fc1c93746e3c7f510e5b3095ea3090e1b8807 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/30991 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-28soc/apollolake: Generate DMAR tableWerner Zeh
Generate DMAR table if VTd feature is enabled. Test=Booted into Linux on mc_apl2 and verified the DMAR table contents. In addition turned off Vtd and verified that no DMAR table is generated at all. Change-Id: Ie3683a2f3578c141c691b2268e32f27ba2e772fa Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/30990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-28soc/intel/{apl,skl}: Drop redundant `select RTC`Nico Huber
RTC is now implicitly selected through SOC_INTEL_COMMON_BLOCK_RTC and SOC_INTEL_COMMON_PCH_BASE. Change-Id: I1885c419cfe318b75f3bda6220d4a6f6a8e26575 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/31113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-01-25soc/intel/apollolake: Override GLK usb clock gating registerJohn Zhao
It was observed system suspend/resume failure while running RunInDozingStress. Apply correct GLK usb clock gating register value to mitigate the failure. BRANCH=octopus BUG=b:120526309 TEST=Verified GLK clock gating register value after booting to kernel. Change-Id: I50fb16f5ab0e28e79f71c7f0f8e75ac8791c0747 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-23soc/{amd,intel}: Remove needless '&' on function pointersElyes HAOUAS
Change-Id: I7a59fd2f370d2b0d830ca83be9a9bc1abe2750f5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
2019-01-16buildsystem: Promote rules.h to default includeKyösti Mälkki
Does not fix 3rdparty/, *.S or *.ld or yet. Change-Id: I66b48013dd89540b35ab219d2b64bc13f5f19cda Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/17656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-15soc/intel/apl: Hook microcode updates upNico Huber
Only tested on APL. Change-Id: I53f680fc4342a9bd1cd0ba9d72e025995e25f7f2 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/29902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-14console: Change BOOTBLOCK_CONSOLE default to `y`Nico Huber
Invert the default instead of selecting it everywhere. Restores the ability to use its Kconfig prompt. Beside Qemu targets, the only platforms that didn't select it seem to be samsung/exynos5420, intel/cannonlake, and intel/icelake. The latter two were about to be patched anyway. Change-Id: I7c5b671b7dddb5c6535c97c2cbb5f5053909dc64 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/30891 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14soc/intel/apollolake: Add option to disable xHCI Link Compliance ModeJohn Zhao
Provide options to disable xHCI Link Compliance Mode. Default is FALSE to not disable Compliance Mode. Set TRUE to disable Compliance Mode. BRANCH=octopus BUG=b:115699781 TEST=Verified booting to kernel. Change-Id: I2a486bc4c1a8578cfd7ac3d17103e889eaa25fe4 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30816 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-10soc/intel/common/block: Move tco common functions into block/smbusSubrata Banik
This patch cleans soc/intel/{apl/cnl/icl/skl} by moving common soc code into common/block/smbus. BUG=b:78109109 BRANCH=NONE TEST=Build and boot KBL/CNL/APL/ICL platform. Change-Id: I34b33922cafee9f31702587e0f9c03b64f0781b8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/26166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-10Untangle CBFS microcode updatesNico Huber
The option to specify a binary file name was added later for platforms that do not provide microcode updates in our blobs repository. Alas, it wasn't visible what platforms these are. And if you specified a file for a platform that already had one, they were all included together. Make it visible which platforms don't provide binaries with the new con- figs MICROCODE_BLOB_NOT_IN_BLOB_REPO, MICROCODE_BLOB_NOT_HOOKED_UP and MICROCODE_BLOB_UNDISCLOSED. Based on that we can decide if we want to include binaries by default or explicitly show that no files are inclu- ded (default to CPU_MICROCODE_CBFS_NONE). Also split CPU_MICROCODE_CBFS_GENERATE into the more explicit CPU_MICROCODE_CBFS_DEFAULT_BINS and CPU_MICROCODE_CBFS_EXTERNAL_BINS. And clean up the visibility of options: Don't show CBFS related options on platforms that don't support it and don't show external file options if the platform uses special rules for multiple files (CPU_MICROCODE_ MULTIPLE_FILES). Change-Id: Ib403402e240d3531640a62ce93b7a93b4ef6ca5e Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/29934 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-09soc/intel: Clean mess around UART_DEBUGNico Huber
Everything is wrong here, the Kconfig symbols are only the tip of the iceberg. Based on Kconfig prompts the SoC code performed pad configu- rations! I don't see why the person who configures coreboot should have the board schematics at hand. As a mitigation, we remove the prompts for UART_DEBUG, which is renamed to INTEL_LPSS_UART_FOR_CONSOLE (because the former didn't really say what it's about), and for UART_FOR_CONSOLE in case the former is selec- ted. Change-Id: Ibe2ed3cab0bb04bb23989c22da45299f088c758b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/29573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-07soc/intel: Standardize names of common MSRsElyes HAOUAS
Use defined name in Intel 64 and IA-32 Architectures Software Developer’s Manual. Renamed MSRs are (register address, register name): 0x35 MSR_CORE_THREAD_COUNT 0x121 MSR_EMULATE_PM_TIMER 0x1f4 MSR_PRMRR_PHYS_BASE 0x1f5 MSR_PRMRR_PHYS_MASK 0x2f4 MSR_UNCORE_PRMRR_PHYS_BASE 0x2f5 MSR_UNCORE_PRMRR_PHYS_MASK Change-Id: I53f11a2ce831456d598aa21303a817d18ac89bba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2018-12-20soc/intel: Get rid of device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: Ic29891d78514db3b7eed48414a14e4ff579436c0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30004 Reviewed-by: David Guckian Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-19soc: Remove useless include <device/pci_ids.h>Elyes HAOUAS
Change-Id: Idef8c556ac8c05c5e2047a38629422544392cd62 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-07soc/intel/apollolake: Print ME version on exit of BS_DEV_INIT stageKarthikeyan Ramasubramanian
Recently there has been a change to print ME version. But the stage at which the version is printed causes the HECI device to remain in D0 state. This in turn prevents the SoC from entering S0ix state. This change moves printing ME version a little earlier so that the HECI device is put into D0i3 state by FSP and the SoC can enter S0ix state successfully. BRANCH=octopus BUG=b:120571529 TEST=Ensure that the ME version gets printed in BIOS logs. Ensure that the device boots to ChromeOS. Ensure that the device enters S0ix successfully(using suspend_stress_test -c 25). Change-Id: I85bc45003a040c8347f929457792d78a9a077c6c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/30074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-06soc/intel/apl: Warn if CBFS is outside the memory mapped areaNico Huber
As part of the memory mapped BIOS region is covered by SRAM, check that CBFS always fits the effectively mapped region of flash. This is usually taken care of by reserving the SRAM range in the FMAP (e.g. as BIOS_UNUSABLE), but can be missed. Change-Id: If5a5b553ad4853723bf13349c809c4f6154aa5f2 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/30055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-04soc/intel/common/dptf: Make CPU address a defineDuncan Laurie
In order to support using the common ACPI code on more platforms than just Apollo Lake the DPTF code needs to be told what the PCI address is for the CPU thermal device. Change-Id: I638f2387330bbc42f64eb0fb676ee32c5df6572e Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29757 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03soc/intel/apl: Enable graphics with libgfxinitNico Huber
Backlight control of internal panels likely won't work as configuration for that seems absent in coreboot. Also, libgfxinit doesn't support any MIPI/DSI connections, yet, and neither Gemini Lake. TEST=Booted work-in-progress port kontron/mal10 with VGA text and linear framebuffer modes. DP display came up. Change-Id: I7b111f1cdac4d18f2fc3089f57aebf3ad1739e5d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/29903 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03soc/intel/apollolake: Add support to print ME versionFurquan Shaikh
This change adds support to print ME version if UART_DEBUG is enabled. Check for UART_DEBUG is necessary because talking to ME to get the firmware version adds ~0.6 seconds to boot time. TEST=Verified on octopus that ME version printed is correct. Change-Id: I41217371558da1af694a2705e005429155d62838 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/29989 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03soc/intel/apl: Configure LPC serial IRQ modeNico Huber
Sync the FSP settings with what coreboot does. Why both FSP and coreboot configure this redundantly stays a secret. TEST=Set SERIRQ_CONTINUOUS on kontron/mal10. A CPLD connected to LPC works correctly now, but was confused by the wrong settings before because the FSP defaults allowed to disable the LPC clock. Change-Id: Id1c7180f460678bf0f9458228591050dd628c052 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/29901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-30cpu/intel/common: Use a common acpi/cpu.asl fileArthur Heymans
Change-Id: Ifa5a3a22771ff2e0efa14fb765603fd5e0440d59 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: David Guckian
2018-11-30soc/intel/common: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications to the CPU. Change-Id: Id64f9857bbd7db520c94de949db8f823f71d6dae Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-11-30security/vboot: Fix remaining measured boot issuesPhilipp Deppenwiese
Makes vboot measured boot mode available for all boards. * Increase Tegra210 and Rockchip3228 SRAM for romstage/verstage. * Add missing files for Intel apollolake and AMD stoneyridge as TPM driver target. Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/29840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-11-23soc/intel/apollolake: Remove cycle in Kconfig symbol dependenciesPatrick Georgi
Change-Id: Iad60a5c8863283b7d373e1f6aaff48c40b7bb274 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/29812 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-23soc/intel/apollolake: Add Kconfig switch to enable minimum clock ratioWerner Zeh
Add a Kconfig switch to be able to set the CPU clock to the lowest possible ratio. If enabled the CPU will consume as little power as possible while providing the lowest performance. This setting can be overruled by the OS if it has an p-state driver which can adjust the clock to its need. Change-Id: I4a59586da72d1915749110a36f565fe2aa69e073 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/29772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-16src: Remove unneeded include <cbfs.h>Elyes HAOUAS
Change-Id: Iab0bd1c5482331a0c048a05ab806bf5c4dbda780 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29303 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16src: Remove unneeded include <console/console.h>Elyes HAOUAS
Change-Id: I40f8b4c7cbc55e16929b1f40d18bb5a9c19845da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16src: Get rid of duplicated includesElyes HAOUAS
Change-Id: I252a1cd77bf647477edb7dddadb7e527de872439 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-09soc/intel/apollolake: Disable HECI1 before jumping to OSFurquan Shaikh
This change disables HECI1 device at the end of boot sequence. It uses the P2SB messaging to disable HECI1 device before hiding P2SB and dropping privilege level. BUG=b:119074978 BRANCH=None TEST=Verified that HECI1 device is not visible in lspci on octopus. Change-Id: Id6abfd0c71a466d0cf8f19ae9b91f1d3446e3d09 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kane Chen <kane.chen@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-11-08soc/intel/apollolake: Improve cold boot and S3 resumeJohn Zhao
FSP 2.0.7.1 provides UPD interface to execute IPC command. Configure PmicPmcIpcCtrl for PMC to program PMIC PCH_PWROK delay from default 100ms to 10ms to improve cold boot and S3 resume performance. BUG=b:118676361 CQ-DEPEND=CL:*703187 TEST=Verified system_resume_firmware_ec time reduction. Change-Id: I05656c9083a855112120b7f1b0ec01c42f582409 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/29363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-07soc/intel/apollolake: Provide interface to update TCC offsetJohn Su
This change provides an interface for apollolake to set TCC before BIOS reset complete happens in romstage. With this change, we can add code to update Tcc in devicetree. BUG=b:117789732 TEST=Match the result from TAT UI Change-Id: I4419d3bbe2628fcb26ef81828d6325fc952dbabc Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-11-05src: Remove unneeded include <arch/ioapic.h>Elyes HAOUAS
Change-Id: Ic08b191ee4dbcc56eb482601aa268394545936ba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29292 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-01src: Add missing include <stdint.h>Elyes HAOUAS
Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-10-31soc/intel/apollolake: Revert the w/a nWR_24 settingJohn Zhao
GLK FSP 2.0.6.0 has properly determined MR1 value during InitializeJedec. Revert the w/a code "odt_config |= nWR_24" in coreboot. BUG=b:118422998 CQ-DEPEND=CL:*703187 TEST=Verified booting to kernel. Change-Id: I6dd3c14b2048259a5518e1f72ff1061b9c5c7dfe Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/29276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-30src: Add missing include <stdint.h>Elyes HAOUAS
Change-Id: I6a9d71e69ed9230b92f0f330875515a5df29fc06 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29312 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-27soc/intel/*: Make FSP header path user configurablePatrick Georgi
Required to compensate for Chrome OS' tree differences Change-Id: I01fe80b55c69ff57da1c96a76bd1d9b5a2d4a9a8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/29293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-25soc/intel: Consolidate FSP CAR setup and teardown codePraveen hodagatta pranesh
This patch adds following changes, - APL, CFL, DENVERTON soc's using same implementation to setup and teardown FSP CAR. Hence cache_as_ram_fsp.S from soc folder is cosolidated into one file and moved to common code CPU car folder. - exit_car_fsp.S is from APL, DNV soc folder is clubbed into one file and moved to common CPU car. - The new file apollolake/fspcar.c is addded to pass tempraminit parameters. - Coffee lake Soc uses FSPT to support Intel Security features like BootGuard verify boot and Measured boot. Add FSP CAR support for CFL by programming tempraminit parameters and add FSP_T_XIP default if FSP_CAR is selected. BUG= None TEST= Build for both CFL RVP11 & RVP8 and verified for successful CAR setup. Build for both leafhill and harcuvar platform by selecting CONFIG_FSP_CAR without errors. Change-Id: I98d2dd9711ddc0d7ea7d1672fba700259ee3a3a9 Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/29209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-23soc/intel/common/block/gpio: Allow GPI to be dual-routedFurquan Shaikh
This change adds new macros to GPIO common library helpers to allow a GPI pad to be dual routed using PAD_CFG_GPI_DUAL_ROUTE. It also adds a helper macro to configure a pad for IRQ and wake. Above macros are guarded using a newly added Kconfig option SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT that is selected only by SoCs that have been validated to allow dual route of GPIs. Currently, this config is selected only for APL/GLK/SKL/KBL that have been validated to work with dual-routing of GPIs for IRQ and wake. BUG=b:117553222 Change-Id: Iaa623d2d78a50f1504e3abe9a47a5a663693aead Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29188 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-23soc/intel/apollolake: Add reset code to postcar stagePatrick Georgi
Also add a test case for that, a config taken from chromiumos with some references to binaries dropped that aren't in our blobs repo (eg audio firmware). Change-Id: I411c0bacefd9345326f26db4909921dddba28237 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/29223 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-30 01:48:46 +0000