coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2017-11-04	sb and soc: Enforce correct offset of member "chromeos" in global_nvs_t	Jonathan Neuschäfer
2017-09-20	soc/intel/baytrail: refactor rtc failure checking	Aaron Durbin
2017-07-13	soc/intel: add IS_ENABLED() around Kconfig symbol references	Martin Roth
2017-07-13	Rename __attribute__((packed)) --> __packed	Stefan Reinauer
2017-02-14	google/rambi: add explicit pull-down for ram-id	Matt DeVillier
2016-07-31	src/soc: Capitalize CPU, ACPI, RAM and ROM	Elyes HAOUAS
2016-07-30	chromeos mainboards: remove chromeos.asl	Aaron Durbin
2016-07-15	soc/intel/baytrail: use common Intel ACPI hardware definitions	Aaron Durbin
2015-11-21	baytrail: add C0 and D0 stepping decode	Ben Gardner
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-05-23	baytrail: Switch to per-device ACPI	Vladimir Serbinenko
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-04-10	baytrail: correct NC pin to GPO pin according to BYT platform design guide	Kane Chen
2015-04-07	baytrail: Change all SoC headers to <soc/headername.h> system	Julius Werner