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coreboot
2560p
820g2
autoport-hsw
broadwell_refcode
e6230
e7240_bdw
haswell-mrc
hp820g1
hp9480m
mec1322
Some coreboot project code with my work
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intel
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baytrail
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ramstage.c
Age
Commit message (
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Author
2019-12-19
src/soc/intel: Remove unused <stdlib.h>
Elyes HAOUAS
2019-01-06
device: Use pcidev_on_root()
Kyösti Mälkki
2018-10-11
src: Move common IA-32 MSRs to <cpu/x86/msr.h>
Elyes HAOUAS
2018-05-24
soc/intel/baytrail: Get rid of device_t
Elyes HAOUAS
2015-11-21
baytrail: add C0 and D0 stepping decode
Ben Gardner
2015-10-31
tree: drop last paragraph of GPL copyright header
Patrick Georgi
2015-05-21
Remove address from GPLv2 headers
Patrick Georgi
2015-04-10
baytrail: add code for supporting 2x ddr refresh rate
Kane Chen
2015-04-07
baytrail: Change all SoC headers to <soc/headername.h> system
Julius Werner
2015-03-10
ACPI: Get S3 resume state from romstage_handoff
Kyösti Mälkki
2014-10-22
baytrail/rambi: S3 support and other updates
Kein Yuan
2014-09-18
rambi/baytrail: ACPI, GPIO, audio, misc updates
Shawn Nematbakhsh
2014-05-10
baytrail: note S3 resume status earlier
Aaron Durbin
2014-05-07
baytrail: initialize common SSC functionality
Aaron Durbin
2014-05-06
baytrail: Add BCLK and IACORE to pattrs
Duncan Laurie
2014-02-27
baytrail: add GNVS to cbmem and set acpi_slp_type
Aaron Durbin
2014-02-17
baytrail: add support to run reference code blob
Aaron Durbin
2014-02-13
baytrail: allow downstream use of SSE instructions
Aaron Durbin
2014-02-03
baytrail: Add GPIO initial configuration infrastructure.
Shawn Nematbakhsh
2014-01-31
baytrail: introduce pattrs
Aaron Durbin