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coreboot
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broadwell_refcode
e6230
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Some coreboot project code with my work
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intel
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baytrail
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romstage
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romstage.c
Age
Commit message (
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Author
2014-05-13
baytrail: snapshot power state in romstage
Aaron Durbin
2014-05-10
baytrail: allow ramstage_cache_location() usage in ramstage
Aaron Durbin
2014-05-07
baytrail: enable caching and prefetching in spi controller
Aaron Durbin
2014-05-07
baytrail: ensure init_chromeos() is called in romstage
Aaron Durbin
2014-05-06
baytrail: add support for S3 resume
Aaron Durbin
2014-02-27
baytrail: increment boot count for elog
Aaron Durbin
2014-02-24
baytrail: initialize chromeos EC if present in romstage
Aaron Durbin
2014-02-16
baytrail: SMM support
Aaron Durbin
2014-02-15
coreboot: infrastructure for different ramstage loaders
Aaron Durbin
2014-02-13
baytrail: add vboot ramstage verification
Aaron Durbin
2014-02-11
baytrail: move early init to before mainboard
Aaron Durbin
2014-02-11
baytrail: set max frequency early in romstage
Aaron Durbin
2014-02-05
baytrail: initialize punit
Aaron Durbin
2014-02-05
baytrail: disable tco timer
Aaron Durbin
2014-02-05
baytrail: program PUNIT memory-mapped base address
Aaron Durbin
2014-02-05
baytrail: start collecting timestamps
Aaron Durbin
2014-01-31
baytrail: initialize graphics before MRC
Aaron Durbin
2014-01-31
baytrail: add initial support
Aaron Durbin