summaryrefslogtreecommitdiff
path: root/src/soc/intel/baytrail/romstage
AgeCommit message (Collapse)Author
2018-01-18security/tpm: Change TPM naming for different layers.Philipp Deppenwiese
* Rename tlcl* to tss* as tpm software stack layer. * Fix inconsistent naming. Change-Id: I206dd6a32dbd303a6d4d987e424407ebf5c518fa Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-18security/tpm: Move tpm TSS and TSPI layer to security sectionPhilipp Deppenwiese
* Move code from src/lib and src/include into src/security/tpm * Split TPM TSS 1.2 and 2.0 * Fix header includes * Add a new directory structure with kconfig and makefile includes Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-17drivers/mrc_cache: move mrc_cache support to driversAaron Durbin
There's nothing intel-specific about the current mrc_cache support. It's logic manages saving non-volatile areas into the boot media. Therefore, expose it to the rest of the system for any and all to use. BUG=b:69614064 Change-Id: I3b331c82a102f88912a3e10507a70207fb20aecc Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-22security/vboot: Move vboot2 to security kconfig sectionPhilipp Deppenwiese
This commit just moves the vboot sources into the security directory and fixes kconfig/makefile paths. Fix vboot2 headers Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-04chromeec: Remove checks for EC in RODaisuke Nojiri
This patch removes checks that ensure EC to be in RO for recovery boot. We do not need these checks because when recovery is requested automatically (as opposed to manually), we show 'broken' screen where users can only reboot the device or request recovery manually. If recovery is requested, Depthcharge will check whether EC is in RO or not and recovery switch was pressed or not. If it's a legitimate manual recovery, EC should be in RO. Thus, we can trust the recovery button state it reports. This patch removes all calls to google_chromeec_check_ec_image, which is called to avoid duplicate memory training when recovery is requested but EC is in RW. BUG=b:66516882 BRANCH=none CQ-DEPEND=CL:693008 TEST=Boot Fizz. Change-Id: I45a874b73c46ea88cb831485757d194faa9f4c99 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/21711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-18vboot: Remove get_sw_write_protect_state callbackJulius Werner
We've just decided to remove the only known use of the VBSD_SW_WP flag in vboot (https://chromium-review.googlesource.com/c/575389), since it was unused and never reliable on all platforms anyway. Therefore, we can now also remove the coreboot infrastructure that supported it. It doesn't really hurt anyone, but removing it saves a small bit of effort for future platforms. Change-Id: I6706eba2761a73482e03f3bf46343cf1d84f154b Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/20628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-13soc/intel: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Change-Id: I3c5f9e0d3d1efdd83442ce724043729c8648ea64 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-12-15soc/intel/common: remove mrc cache assumptionsAaron Durbin
Update the mrc cache implementation to use region_file. Instead of relying on memory-mapped access and pointer arithmetic use the region_devices and region_file to obtain the latest data associated with the region. This removes the need for the nvm wrapper as the region_devices can be used directly. Thus, the library is more generic and can be extended to work on different boot mediums. BUG=chrome-os-partner:56151 Change-Id: Ic14e2d2f7339e50256b4a3a297fc33991861ca44 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17717 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-01lib: put romstage_handoff implementation in own compilation unitAaron Durbin
Instead of putting all the functions inline just put the current implementation into a C file. That way all the implementation innards are not exposed. Lastly, fix up the fallout of compilation units not including the headers they actually use. Change-Id: I01fd25d158c0d5016405b73a4d4df3721c281b04 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17648 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-01romstage_handoff: remove code duplicationAaron Durbin
The same pattern was being used throughout the code base for initializing the romstage handoff structure. Provide a helper function to initialize the structure with the S3 resume state then utilize it at all the existing call sites. Change-Id: I1e9d588ab6b9ace67757387dbb5963ae31ceb252 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17646 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-11-18intel post-car: Increase stacktop alignmentKyösti Mälkki
Align top of stack to 8 bytes, value documented as FSP1.1 requirement. Also fix some cases of uintptr_t casted to unsigned long. Change-Id: I5bbd100eeb673417da205a2c2c3410fef1af61f0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17461 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-31lib/prog_loaders: use common ramstage_cache_invalid()Aaron Durbin
All current implementations of ramstage_cache_invalid() were just resetting the system based on the RESET_ON_INVALID_RAMSTAGE_CACHE Kconfig option. Move that behavior to a single implementation within prog_loaders.c which removes duplication. Change-Id: I67aae73f9e1305732f90d947fe57c5aaf66ada9e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17184 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-31src/soc: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: Ifc47f103492a2cd6c818dfd64be971d34afbe0a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16324 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-31src/soc: Capitalize CPU, ACPI, RAM and ROMElyes HAOUAS
Change-Id: I7f0d3400126d593bad8e78f95e6b9a378463b4ce Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15963 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-28bootmode: Get rid of CONFIG_BOOTMODE_STRAPSFurquan Shaikh
With VBOOT_VERIFY_FIRMWARE separated from CHROMEOS, move recovery and developer mode check functions to vboot. Thus, get rid of the BOOTMODE_STRAPS option which controlled these functions under src/lib. BUG=chrome-os-partner:55639 Change-Id: Ia2571026ce8976856add01095cc6be415d2be22e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15868 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15soc/intel/baytrail: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: Idf055fa86b56001a805e139de6723dfb77dcb224 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15669 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-10intel post-car: Consolidate choose_top_of_stack()Kyösti Mälkki
Change-Id: I2c49d68ea9a8f52737b6064bc4fa703bdb1af1df Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15463 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-29intel romstage: Use run_ramstage()Kyösti Mälkki
Change-Id: I22a33e6027a4e807f7157a0dfafbd6377bc1285d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15461 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22Ignore RAMTOP for MTRRsKyösti Mälkki
Without RELOCATABLE_RAMSTAGE have WB cache large enough to cover the greatest ramstage needs, as there is no benefit of trying to accurately match the actual need. Choose this to be bottom 16MiB. With RELOCATABLE_RAMSTAGE write-back cache of low ram is only useful for bottom 1MiB of RAM as a small part of this gets used during SMP initialisation before proper MTRR setup. Change-Id: Icd5f8461f81ed0e671130f1142641a48d1304f30 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15249 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-18intel cache_as_ram: Fix typo in commentKyösti Mälkki
Change-Id: I2539e490e160e01cab2ad8d2086d2f242a88c640 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15223 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-17Fix some cbmem.h includesKyösti Mälkki
Change-Id: I36056af9f2313eff835be805c8479e81d0b742bf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15196 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-03intel/baytrail: use fmap information for code cachingPatrick Georgi
Instead of using CBFS_SIZE from Kconfig, use values generated from fmap. While at it, make sure that the cached region size is a power of two. fmap_config is also added to cpu_incs-y, but that doesn't hurt (except for some miniscule increase in compile time) because it's #if-guarded. The upside is that dependencies are tracked properly. Change-Id: I03a919e1381ca3d0e972780b2c7d76c590aaa994 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14573 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-26tree wide: Convert "if (CONFIG_.*_TPM.*)" to "if (IS_ENABLED(...))"Denis 'GNUtoo' Carikli
Change-Id: Ib73abb0ada7dfdfab3487c005719e19f51ef1812 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: https://review.coreboot.org/13779 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-15cpu/mtrr.h: Fix macro names for MTRR registersAlexandru Gagniuc
We use UNDERSCORE_CASE. For the MTRR macros that refer to an MSR, we also remove the _MSR suffix, as they are, by definition, MSRs. Change-Id: Id4483a75d62cf1b478a9105ee98a8f55140ce0ef Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11761 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-09-24coreboot: move TS_END_ROMSTAGE to one spotAaron Durbin
While the romstage code flow is not consistent across all mainboards/chipsets there is only one way of running ramstage from romstage -- run_ramstage(). Move the timestamp_add_now(TS_END_ROMSTAGE) to be within run_ramstage(). BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. TS_END_ROMSTAGE still present in timestamp table. Change-Id: I4b584e274ce2107e83ca6425491fdc71a138e82c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11700 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-23chromeos: vboot and chromeos dependency removal for sw write protect statePaul Kocialkowski
This removes the dependency on chromeos and vboot for the sw write protect state function: vboot_get_sw_write_protect, renamed to get_sw_write_protect_state to both reflect this change and become consistent with the definition of get_write_protect_state that is already in use. Change-Id: I47ce31530a03f6749e0f370e5d868466318b3bb6 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: http://review.coreboot.org/11496 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-04x86: remove cpu_incs as romstage Make variableAaron Durbin
When building up which files to include in romstage there were both 'cpu_incs' and 'cpu_incs-y' which were used to generate crt0.S. Remove the former to settle on cpu_incs-y as the way to be included. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi. No include file changes. Change-Id: I8dc0631f8253c21c670f2f02928225ed5b869ce6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11494 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-07x86: Drop -Wa,--divideStefan Reinauer
Fix up all the code that is using / to use >> for divisions instead. Change-Id: I8a6deb0aa090e0df71d90a5509c911b295833cea Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10819 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-09stage_cache: use cbmem init hooksAaron Durbin
Instead of having the chipset code make the approrpiate calls at the appropriate places use the cbmem init hooks to take the appropriate action. That way no chipset code needs to be changed in order to support the external stage cache. Change-Id: If74e6155ae86646bde02b2e1b550ade92b8ba9bb Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10481 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-09cbmem: add indicator to hooks if cbmem is being recoveredAaron Durbin
It can be helpful to certain users of the cbmem init hooks to know if recovery was done or not. Therefore, add this as a parameter to the hooks. Change-Id: I049fc191059cfdb8095986d3dc4eee9e25cf5452 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10480 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-09cbmem: Unify CBMEM init tasks with CBMEM_INIT_HOOK() APIKyösti Mälkki
Squashed and adjusted two changes from chromium.git. Covers CBMEM init for ROMTAGE and RAMSTAGE. cbmem: Unify random on-CBMEM-init tasks under common CBMEM_INIT_HOOK() API There are several use cases for performing a certain task when CBMEM is first set up (usually to migrate some data into it that was previously kept in BSS/SRAM/hammerspace), and unfortunately we handle each of them differently: timestamp migration is called explicitly from cbmem_initialize(), certain x86-chipset-specific tasks use the CAR_MIGRATION() macro to register a hook, and the CBMEM console is migrated through a direct call from romstage (on non-x86 and SandyBridge boards). This patch decouples the CAR_MIGRATION() hook mechanism from cache-as-RAM and rechristens it to CBMEM_INIT_HOOK(), which is a clearer description of what it really does. All of the above use cases are ported to this new, consistent model, allowing us to have one less line of boilerplate in non-CAR romstages. BRANCH=None BUG=None TEST=Built and booted on Nyan_Blaze and Falco with and without CONFIG_CBMEM_CONSOLE. Confirmed that 'cbmem -c' shows the full log after boot (and the resume log after S3 resume on Falco). Compiled for Parrot, Stout and Lumpy. Original-Change-Id: I1681b372664f5a1f15c3733cbd32b9b11f55f8ea Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/232612 Reviewed-by: Aaron Durbin <adurbin@chromium.org> cbmem: Extend hooks to ramstage, fix timestamp synching Commit 7dd5bbd71 (cbmem: Unify random on-CBMEM-init tasks under common CBMEM_INIT_HOOK() API) inadvertently broke ramstage timestamps since timestamp_sync() was no longer called there. Oops. This patch fixes the issue by extending the CBMEM_INIT_HOOK() mechanism to the cbmem_initialize() call in ramstage. The macro is split into explicit ROMSTAGE_/RAMSTAGE_ versions to make the behavior as clear as possible and prevent surprises (although just using a single macro and relying on the Makefiles to link an object into all appropriate stages would also work). This allows us to get rid of the explicit cbmemc_reinit() in ramstage (which I somehow accounted for in the last patch without realizing that timestamps work exactly the same way...), and replace the older and less flexible cbmem_arch_init() mechanism. Also added a size assertion for the pre-RAM CBMEM console to memlayout that could prevent a very unlikely buffer overflow I just noticed. BRANCH=None BUG=None TEST=Booted on Pinky and Falco, confirmed that ramstage timestamps once again show up. Compile-tested for Rambi and Samus. Original-Change-Id: If907266c3f20dc3d599b5c968ea5b39fe5c00e9c Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/233533 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I1be89bafacfe85cba63426e2d91f5d8d4caa1800 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7878 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-08Remove empty lines at end of fileElyes HAOUAS
Used command line to remove empty lines at end of file: find . -type f -exec sed -i -e :a -e '/^\n*$/{$d;N;};/\n$/ba' {} \; Change-Id: I816ac9666b6dbb7c7e47843672f0d5cc499766a3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/10446 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-02cbfs: new API and better program loadingAaron Durbin
A new CBFS API is introduced to allow making CBFS access easier for providing multiple CBFS sources. That is achieved by decoupling the cbfs source from a CBFS file. A CBFS source is described by a descriptor. It contains the necessary properties for walking a CBFS to locate a file. The CBFS file is then decoupled from the CBFS descriptor in that it's no longer needed to access the contents of the file. All of this is accomplished using the regions infrastructure by repsenting CBFS sources and files as region_devices. Because region_devices can be chained together forming subregions this allows one to decouple a CBFS source from a file. This also allows one to provide CBFS files that came from other sources for payload and/or stage loading. The program loading takes advantage of those very properties by allowing multiple sources for locating a program. Because of this we can reduce the overhead of loading programs because it's all done in the common code paths. Only locating the program is per source. Change-Id: I339b84fce95f03d1dbb63a0f54a26be5eb07f7c8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9134 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-27Move TPM code out of chromeosVladimir Serbinenko
This code is not specific to ChromeOS and is useful outside of it. Like with small modifications it can be used to disable TPM altogether. Change-Id: I8c6baf0a1f7c67141f30101a132ea039b0d09819 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10269 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-04-22coreboot: common stage cacheAaron Durbin
Many chipsets were using a stage cache for reference code or when using a relocatable ramstage. Provide a common API for the chipsets to use while reducing code duplication. Change-Id: Ia36efa169fe6bd8a3dbe07bf57a9729c7edbdd46 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8625 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-07baytrail: Change all SoC headers to <soc/headername.h> systemJulius Werner
This patch aligns baytrail to the new SoC header include scheme. BUG=None TEST=Tested with whole series. Compiled Rambi. Change-Id: I0f0a894f6f33449756582eefa0b50bae545220db Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1216a86538517c03a7e5bca547d08ff3dbcaa083 Original-Change-Id: If5d2a609354b3d773aa3d482e682ab97422fd9d5 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/222026 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9363 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-04-01cbfs: correct types used for accessing filesAaron Durbin
In commit 72a8e5e751a7fa97c9d198f68cad49f9d9851669 the Makefile's were updated to use named types for cbfs file addition. However, the call sites were not checked to ensure the types matched. Correct all call sites to use the named types. Change-Id: Ib9fa693ef517e3196a3f04e9c06db52a9116fee7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9195 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-15x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointerKevin Paul Herbert
On x86, change the type of the address parameter in read8()/read16/read32()/write8()/write16()/write32() to be a pointer, instead of unsigned long. Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7784 Tested-by: build bot (Jenkins)
2015-01-14baytrail broadwell: Use timestamps internal stashKyösti Mälkki
No reason to carry timestamps on CAR stack, as implementation of timestamps internally stashes on CAR_GLOBAL table and migrates those to CBMEM. Change-Id: I5b3307df728b18cd7ebf3352f7f7e270ed1e9002 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8022 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2015-01-05timestamps: Switch from tsc_t to uint64_tStefan Reinauer
Cherry-pick from chromium and adjusted for added boards and changed directory layout for arch/arm. Timestamp implementation for ARMv7 Abstract the use of rdtsc() and make the timestamps uint64_t in the generic code. The ARM implementation uses the monotonic timer. Original-Signed-off-by: Stefan Reinauer <reinauer@google.com> BRANCH=none BUG=chrome-os-partner:18637 TEST=See cbmem print timestamps Original-Change-Id: Id377ba570094c44e6895ae75f8d6578c8865ea62 Original-Reviewed-on: https://gerrit.chromium.org/gerrit/63793 (cherry-picked from commit cc1a75e059020a39146e25b9198b0d58aa03924c) Change-Id: Ic51fb78ddd05ba81906d9c3b35043fa14fbbed75 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8020 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-11-30Replace hlt() loops with halt()Patrick Georgi
Change-Id: I8486e70615f4c404a342cb86963b5357a934c41d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7606 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-28baytrail: handle MRC being an ELF fileAaron Durbin
Provide the option to embed MRC as an ELF file and not just binary blob. This allows for MRC to be relocated. BUG=chrome-os-partner:27654 BRANCH=rambi TEST=Built and booted rambi. Change-Id: I2e177c155a3074e4e1d450b1a73b7299aebd5286 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/192893 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit 89c97d5e2023b8c5cc780e1b1d532d0a586512f9) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7214 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-10-28baytrail: romstage: Add function to check SW WP status for vbootShawn Nematbakhsh
Implement vboot_get_sw_write_protect, which returns the FW SPI ROM SW WP status. BUG=chrome-os-partner:26777 TEST=Manual on Rambi with all patches in sequence: `crossystem sw_wpsw_boot` prints 0 `flashrom --wp-enable` + reboot `crossystem sw_wpsw_boot` prints 1 BRANCH=Rambi Original-Change-Id: I5da35c1b2d25b8679bf0084af65d08de224387f8 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/190097 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 5bba447654417c42952c49542ed047b4867d04d1) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I739cbb8fca5f02462cf78c81f9b364aabfd3fe86 Reviewed-on: http://review.coreboot.org/7211 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-22baytrail: Move MRC cache code to a common directoryDuncan Laurie
This common code can be shared across Intel SOCs. Change-Id: Id9ec4ccd3fc81cbab19a7d7e13bfa3975d9802d0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/196263 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit f9919e2551b02056b83918d2e7b515b25541c583) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6967 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-19x86 romstage: Move stack just below RAMTOPKyösti Mälkki
Placement of romstage stack in RAM was vulnerable for getting corrupted by decompressed ramstage. Change-Id: Ic032bd3e69f4ab8dab8e5932df39fab70aa3e769 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7096 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-09-19baytrail/rambi: spi, charger, and audio updatesAaron Durbin
baytrail: combine SPI configuration in romstage Reviewed-on: https://chromium-review.googlesource.com/185140 (cherry picked from commit 4e7f0e8ae1138e478ae7106d54719cf05e13b402) baytrail: lock down registers before handoff Reviewed-on: https://chromium-review.googlesource.com/185200 (cherry picked from commit 82cce4d2b46ccc554b71efa179b5d95756e2ad5e) baytrail: invoke SMM finalization on handoff Reviewed-on: https://chromium-review.googlesource.com/185201 (cherry picked from commit 1b50affb1fdda52a5986c9429713930ed517a86a) rambi: don't invoke SMM finalization Reviewed-on: https://chromium-review.googlesource.com/185202 (cherry picked from commit 6eff475dae7f4536eb846ccf6d51fce262b8ffef) rambi: remove handling of APM_CNT_FINALIZE Reviewed-on: https://chromium-review.googlesource.com/185203 (cherry picked from commit 9fc310d7e2730466cc7fcc84999502a2d4d08bab) baytrail: don't increment boot count on S3 resume Reviewed-on: https://chromium-review.googlesource.com/185381 (cherry picked from commit 940a0fa4df1ce335229eb6f80143b93a84ba358c) rambi: enable HDA device Reviewed-on: https://chromium-review.googlesource.com/184574 (cherry picked from commit 334f2a5c7c6540e744b6aaf7e1da0b55e1368196) baytrail: lock down spi controller according to mainboard Reviewed-on: https://chromium-review.googlesource.com/185631 (cherry picked from commit 696ece68cb6d522c248e800f168e675e4b4a7317) rambi: implement mainboard_get_spi_config() to lock dow spi controller Reviewed-on: https://chromium-review.googlesource.com/185632 (cherry picked from commit 1d9ba15858fd421a4fe5a47f7171273128e89524) baytrail: introduce ssus_disable_internal_pull() Reviewed-on: https://chromium-review.googlesource.com/185740 (cherry picked from commit 9d6056dd70b27183dab6a4656f4f9612ae870a4d) rambi: fix write-protect gpio reading at romstage Reviewed-on: https://chromium-review.googlesource.com/185741 (cherry picked from commit c64627689b1afec59be6fdab323d5492046f0bc7) baytrail: DPTF: implement charger current limit Reviewed-on: https://chromium-review.googlesource.com/185759 (cherry picked from commit 287e8936613a7a83281ff692b20383dacf7fcaf6) rambi: Enable charger participant and define states Reviewed-on: https://chromium-review.googlesource.com/185760 (cherry picked from commit 2f62a11927ecf10cb2c76a9f5d368d4050404137) baytrail: increase command wait timeout Reviewed-on: https://chromium-review.googlesource.com/185874 (cherry picked from commit 962a79ef72169b5d52fc746d1889d3b652fd9bcc) baytrail: make caching MRC data more robust Reviewed-on: https://chromium-review.googlesource.com/185875 (cherry picked from commit b5e10ad47b9e4f330caaee4faf69702f24d6bdd8) baytrail: upgrade MRC wrapper header Reviewed-on: https://chromium-review.googlesource.com/186391 (cherry picked from commit 8c1a62f1f4261d4f38aacbbb353c9d6218ec2885) rambi: instruct MRC to use weaker memory ODT settings Reviewed-on: https://chromium-review.googlesource.com/186420 (cherry picked from commit b9329126ca08d20ce1d8c5db0fcabd39140c7292) rambi: Move touch wakeup resource GPIO to separate device Reviewed-on: https://chromium-review.googlesource.com/186932 (cherry picked from commit ba44e2e04f9469c629cb61a911c8cd339f52b0ef) baytrail: Set some MSRs related to turbo power Reviewed-on: https://chromium-review.googlesource.com/186933 (cherry picked from commit 76b25df5a31914ae58d47d17af448216011e425c) baytrail: change power consumption number for ACPI_C3/C6FS. Reviewed-on: https://chromium-review.googlesource.com/186934 (cherry picked from commit 5192e2464fbb88ea6fc117070240c9733e34f065) baytrail: Fix use of ConcatenateResTemplate() in ACPI LPE device Reviewed-on: https://chromium-review.googlesource.com/186928 (cherry picked from commit 8d1ab5de1d43b0790d140f6d0e36a990a5049ece) baytrail: Disable P-state HW coordination on 4-core SKU Reviewed-on: https://chromium-review.googlesource.com/187575 (cherry picked from commit c19c0f1d7cb3cb2635766c186ba9598933424a78) baytrail: DPTF: Enable mainboard-specific _PDL Reviewed-on: https://chromium-review.googlesource.com/187576 (cherry picked from commit 5412ac5c07bee22017a0ee6d1e2433917b98ea87) rambi: Apply DPTF tuning parameters Reviewed-on: https://chromium-review.googlesource.com/187577 (cherry picked from commit 932a5a3803ceaf430ad2934b371ac0886c25efca) rambi : change lpe_codec_clk_freq to 19.2 Reviewed-on: https://chromium-review.googlesource.com/187594 (cherry picked from commit f64cb1ae77076ad5ec994670f4a83dc561ea80c4) Squashed 25 commits for baytrail/rambi. Change-Id: Ibe628ac974d117a09361f7f3131a488911ddd27d Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6933 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2014-09-18rambi/baytrail: ACPI, GPIO, audio, misc updatesShawn Nematbakhsh
rambi: Change RAM_ID GPIOs to GPIO_INPUT Reviewed-on: https://chromium-review.googlesource.com/182934 (cherry picked from commit 8afd981a091a3711ff3b55520fe73f57f7258cc0) baytrail: initialize rtc device Reviewed-on: https://chromium-review.googlesource.com/183051 (cherry picked from commit 1b80d71e4942310bd7e83c5565c6a06c30811821) baytrail: Set SOC power budget values for SdpProfile 2&3 Reviewed-on: https://chromium-review.googlesource.com/183101 (cherry picked from commit 87d49323cac4492c23f910bd7d43b83b3c8a9b55) baytrail: Set PMC PTPS register correctly Reviewed-on: https://chromium-review.googlesource.com/183280 (cherry picked from commit 1b520b577f2bf1b124db301f57421665b637f9ad) baytrail: update to version 809 microcode for c0 Reviewed-on: https://chromium-review.googlesource.com/183256 (cherry picked from commit 8ed0ef4c3bed1196256c691be5b80563b81baa5e) baytrail: Add a shared GNVS init function Reviewed-on: https://chromium-review.googlesource.com/183332 (cherry picked from commit 969dffda1d3d0adaee58d604b6eeea13a41a408c) baytrail: Add basic support for ACPI System Wake Source Reviewed-on: https://chromium-review.googlesource.com/183333 (cherry picked from commit a6b85ad950fb3a51d12cb91c869420b72b433619) baytrail: allow configuration of io hole size Reviewed-on: https://chromium-review.googlesource.com/183269 (cherry picked from commit 95a79aff57ec7bf4bcbf0207a017c9dab10c1919) baytrail: add in C0 stepping idenitification support. Reviewed-on: https://chromium-review.googlesource.com/183594 (cherry picked from commit 8ad02684b25f2870cdea334fbd081f0ef4467cd4) baytrail: add option for enabling PS2 mode Reviewed-on: https://chromium-review.googlesource.com/183595 (cherry picked from commit c92db75de5edc2ff745c1d40155e8b654ad3d49f) rambi: enable PS2 mode for VNN and VCC Reviewed-on: https://chromium-review.googlesource.com/183596 (cherry picked from commit 821ce0e72c93adb60404a4dc4ff8c0f6285cbdf9) baytrail: add config option for disabling slp_x stretching Reviewed-on: https://chromium-review.googlesource.com/183587 (cherry picked from commit f99804c2649bef436644dd300be2a595659ceece) rambi: disable slp_x stretching after sus fail Reviewed-on: https://chromium-review.googlesource.com/183588 (cherry picked from commit 753fadb6b9e90fc8d1c5092d50b20a2826d8d880) baytrail: ACPI_ENABLE_WAKE_SUS_GPIO macro for ACPI Reviewed-on: https://chromium-review.googlesource.com/183597 (cherry picked from commit 78775098a87f46b3bb66ade124753a195a5fa906) rambi: fix trackpad and touchscreen wake sources Reviewed-on: https://chromium-review.googlesource.com/183598 (cherry picked from commit 3022c82b020f4cafeb5be7978eef6045d1408cd5) baytrail: Add support for LPE device in ACPI mode Reviewed-on: https://chromium-review.googlesource.com/184006 (cherry picked from commit 398387ed75a63ce5a6033239ac24b5e1d77c8c9f) rambi: Add LPE GPIOs for Jack/Mic detect Reviewed-on: https://chromium-review.googlesource.com/184007 (cherry picked from commit edde584bb23bae1e703481e0f33a1f036373a578) rambi: Set TSRx passive threshold to 60C Reviewed-on: https://chromium-review.googlesource.com/184008 (cherry picked from commit 1d6aeb85fd1af64d5f7c564c6709a1cf6daad5ee) baytrail: DPTF: Add PPCC object for power limit information Reviewed-on: https://chromium-review.googlesource.com/184158 (cherry picked from commit e9c002c393d8b4904f9d57c5c8e7cf1dfce5049b) baytrail: DPTF: Add _CRT/_PSV objects for the CPU participant Reviewed-on: https://chromium-review.googlesource.com/184442 (cherry picked from commit e04c20962aede1aa9e6899bd3072daa82e8613bd) rambi: Move the CPU passive/critical threshold config to DPTF Reviewed-on: https://chromium-review.googlesource.com/184443 (cherry picked from commit dda468793143a6d288981b6d7e1cd5ef4514c2ac) baytrail: Fix XHCI controller reset on resume Reviewed-on: https://chromium-review.googlesource.com/184500 (cherry picked from commit 0457b5dce1860709fcce1407e42ae83023b463cd) baytrail: update lpe audio firmware location Reviewed-on: https://chromium-review.googlesource.com/184481 (cherry picked from commit 0472e6bd45cb069fbe4939c6de499e03c3707ba6) rambi: Put LPSS devices in ACPI mode Reviewed-on: https://chromium-review.googlesource.com/184530 (cherry picked from commit 52bec109860b95e2d6260d5433f33d0923a05ce1) baytrail: initialize HDA device and HDMI codec Reviewed-on: https://chromium-review.googlesource.com/184710 (cherry picked from commit 393198705034aa9c6935615dda6eba8b6bd5c961) baytrail: provide GPIO_ACPI_WAKE configuration Reviewed-on: https://chromium-review.googlesource.com/184718 (cherry picked from commit 44558c3346f5b96cf7b3dcb25a23b4e99855497b) rambi: configure wake pins as just wake sources Reviewed-on: https://chromium-review.googlesource.com/184719 (cherry picked from commit ee4620a90a131dce49f96b2da7f0a3bb70b13115) baytrail: I2C: Add config data to ACPI Device Reviewed-on: https://chromium-review.googlesource.com/184922 (cherry picked from commit ffb73af007e77faf497fbc3321c8163d18c24ec8) Squashed 28 commits for rambi and baytrail. Change-Id: If6060681bb5dc9432a54e6f3c6af9d8080debad8 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6916 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-07-08soc: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: I1829c77f41cc809b590d00ef5522f368bd5fd814 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6208 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-27 06:34:31 +0000