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path: root/src/soc/intel/baytrail
AgeCommit message (Expand)Author
2015-05-21Remove address from GPLv2 headersPatrick Georgi
2015-05-13baytrail: broadwell: correct refcode loadingAaron Durbin
2015-05-053rdparty: move to 3rdparty/blobsPatrick Georgi
2015-05-053rdparty: Move to blobsPatrick Georgi
2015-05-01intel: Correct MMIO related ACPI table settingsDave Frodin
2015-04-30kbuild: Don't require intel/common changes for every socStefan Reinauer
2015-04-29kbuild: automatically include SOCsStefan Reinauer
2015-04-22coreboot: common stage cacheAaron Durbin
2015-04-15soc/baytrail: Use microcode from the blobs repositoryMarc Jones
2015-04-10baytrail: correct NC pin to GPO pin according to BYT platform design guideKane Chen
2015-04-10baytrail: add code for supporting 2x ddr refresh rateKane Chen
2015-04-10baytrail: fix the coding error on PCIe L1 exit latencyKevin L Lee
2015-04-10Baytrail: Prior to PCI scan, wait for LCTL to be active in 50 msKevin Hsieh
2015-04-10baytrail: Switch from ACPI mode to PCI mode for legacy supportMarc Jones
2015-04-07baytrail: Change all SoC headers to <soc/headername.h> systemJulius Werner
2015-04-06baytrail: Fix hdmi audio choppy issueKein Yuan
2015-04-06baytrail: reinitialize spi controller in SMM finalizationAaron Durbin
2015-04-04Baytrail: Fix no_dev_behind_port not executed for RP1/2/3.Kenji Chen
2015-04-03rmodule: use struct prog while loading rmodulesAaron Durbin
2015-04-02baytrail: Change USB3 PLL VCO and iCLK PLL current on BYT-M/D CPUKein Yuan
2015-04-02Baytrail: Change PCIe root disable algorithmKenji Chen
2015-04-02Baytrail: add _PRT to each PCIe root port deviceTed Kuo
2015-04-01cbfs: correct types used for accessing filesAaron Durbin
2015-03-30baytrail: fix HAVE_REFCODE_BLOB build errorsAaron Durbin
2015-03-30Update hex values to CBFS binary name types in MakefilesMartin Roth
2015-03-18bootstate: use structure pointers for scheduling callbacksAaron Durbin
2015-03-10ACPI: Get S3 resume state from romstage_handoffKyösti Mälkki
2015-03-09coreboot: fix munged license textAaron Durbin
2015-02-25soc/intel/baytrail/Kconfig: Remove explicit `HAVE_MONOTONIC_TIMER`Paul Menzel
2015-02-16acpi: Generate valid ACPI processor objectsTimothy Pearson
2015-02-15x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointerKevin Paul Herbert
2015-01-27CBMEM: Always use DYNAMIC_CBMEMKyösti Mälkki
2015-01-27CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEMKyösti Mälkki
2015-01-27vboot2: add verstageStefan Reinauer
2015-01-16baytrail: there is a chance that USBPHY_COMPBG is set to 0Kane Chen
2015-01-16baytrail: use the setting in devicetree.cb to config USBPHY_COMPBGKane Chen
2015-01-14baytrail broadwell: Use timestamps internal stashKyösti Mälkki
2015-01-05timestamps: Switch from tsc_t to uint64_tStefan Reinauer
2014-12-31baytrail: add more gpio init macrosKane Chen
2014-12-30baytrail: Add defines and functions for GPNCOREKein Yuan
2014-12-28intel baytrail broadwell: Include microcode updatesKyösti Mälkki
2014-12-19baytrail SOCs: Add missing comma in gpio.hMartin Roth
2014-12-17baytrail: initialize backlight PWM frequencyAaron Durbin
2014-12-17x86: Initialize SPI controller explicitly during PCH initDavid Hendricks
2014-12-09spi: Eliminate the spi_cs_activate and spi_cs_deactivate functions.Gabe Black
2014-12-09spi: Remove the spi_set_speed and spi_cs_is_valid functions.Gabe Black
2014-12-08intel/baytrail: Spelling fixesMartin Roth
2014-12-02Replace hlt with halt()Patrick Georgi
2014-11-30Replace hlt() loops with halt()Patrick Georgi
2014-11-25intel: Remove IRQ1 from possible PIRQ assignemnt.Vladimir Serbinenko
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