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path: root/src/soc/intel/baytrail
AgeCommit message (Expand)Author
2015-04-02baytrail: Change USB3 PLL VCO and iCLK PLL current on BYT-M/D CPUKein Yuan
2015-04-02Baytrail: Change PCIe root disable algorithmKenji Chen
2015-04-02Baytrail: add _PRT to each PCIe root port deviceTed Kuo
2015-04-01cbfs: correct types used for accessing filesAaron Durbin
2015-03-30baytrail: fix HAVE_REFCODE_BLOB build errorsAaron Durbin
2015-03-30Update hex values to CBFS binary name types in MakefilesMartin Roth
2015-03-18bootstate: use structure pointers for scheduling callbacksAaron Durbin
2015-03-10ACPI: Get S3 resume state from romstage_handoffKyösti Mälkki
2015-03-09coreboot: fix munged license textAaron Durbin
2015-02-25soc/intel/baytrail/Kconfig: Remove explicit `HAVE_MONOTONIC_TIMER`Paul Menzel
2015-02-16acpi: Generate valid ACPI processor objectsTimothy Pearson
2015-02-15x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointerKevin Paul Herbert
2015-01-27CBMEM: Always use DYNAMIC_CBMEMKyösti Mälkki
2015-01-27CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEMKyösti Mälkki
2015-01-27vboot2: add verstageStefan Reinauer
2015-01-16baytrail: there is a chance that USBPHY_COMPBG is set to 0Kane Chen
2015-01-16baytrail: use the setting in devicetree.cb to config USBPHY_COMPBGKane Chen
2015-01-14baytrail broadwell: Use timestamps internal stashKyösti Mälkki
2015-01-05timestamps: Switch from tsc_t to uint64_tStefan Reinauer
2014-12-31baytrail: add more gpio init macrosKane Chen
2014-12-30baytrail: Add defines and functions for GPNCOREKein Yuan
2014-12-28intel baytrail broadwell: Include microcode updatesKyösti Mälkki
2014-12-19baytrail SOCs: Add missing comma in gpio.hMartin Roth
2014-12-17baytrail: initialize backlight PWM frequencyAaron Durbin
2014-12-17x86: Initialize SPI controller explicitly during PCH initDavid Hendricks
2014-12-09spi: Eliminate the spi_cs_activate and spi_cs_deactivate functions.Gabe Black
2014-12-09spi: Remove the spi_set_speed and spi_cs_is_valid functions.Gabe Black
2014-12-08intel/baytrail: Spelling fixesMartin Roth
2014-12-02Replace hlt with halt()Patrick Georgi
2014-11-30Replace hlt() loops with halt()Patrick Georgi
2014-11-25intel: Remove IRQ1 from possible PIRQ assignemnt.Vladimir Serbinenko
2014-11-18baytrail: fix range checkPatrick Georgi
2014-11-13intel: use crosscompiler readelf, instead of globalPatrick Georgi
2014-11-09src: Too many terminators ';;' at end of stmts, stop SkynetEdward O'Callaghan
2014-11-01{cpu,soc}: Use DEVICE_NOOP macro over dummy symbolEdward O'Callaghan
2014-10-28baytrail: Remove unused devicetree fieldsShawn Nematbakhsh
2014-10-28baytrail: gfx: Don't configure hotplug + backlight registersShawn Nematbakhsh
2014-10-28Baytrail/dptf: Always return 0 in TCPU._PPCKein Yuan
2014-10-28baytrail: handle MRC being an ELF fileAaron Durbin
2014-10-28baytrail: Configure MSR for 2-core and 4-core P-state configutationDuncan Laurie
2014-10-28baytrail: move cache-as-ram base address to 0xfe000000Aaron Durbin
2014-10-28baytrail: romstage: Add function to check SW WP status for vbootShawn Nematbakhsh
2014-10-22reg_script: default to n for ARCH_X86Isaac Christensen
2014-10-22cmos: Rename the CMOS related functions.Gabe Black
2014-10-22baytrail: Move HDA verb table to Intel SOC common directoryDuncan Laurie
2014-10-22baytrail: Move MRC cache code to a common directoryDuncan Laurie
2014-10-22baytrail/rambi: S3 support and other updatesKein Yuan
2014-10-19x86 romstage: Move stack just below RAMTOPKyösti Mälkki
2014-10-19haswell baytrail: Enable RELOCATABLE_RAMSTAGEKyösti Mälkki
2014-10-14baytrail: Add padding to the end of device_nvs to match ACPIScott Radcliffe
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