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coreboot
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broadwell_refcode
e6230
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haswell-mrc
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Some coreboot project code with my work
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baytrail
Age
Commit message (
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Author
2015-06-09
stage_cache: use cbmem init hooks
Aaron Durbin
2015-06-09
cbmem: add indicator to hooks if cbmem is being recovered
Aaron Durbin
2015-06-09
cbmem: Unify CBMEM init tasks with CBMEM_INIT_HOOK() API
Kyösti Mälkki
2015-06-08
Remove empty lines at end of file
Elyes HAOUAS
2015-06-05
device_ops: add device_t argument to acpi_fill_ssdt_generator
Alexander Couzens
2015-06-05
device_ops: add device_t argument to acpi_inject_dsdt_generator
Alexander Couzens
2015-06-04
devicetree: Change scan_bus() prototype in device ops
Kyösti Mälkki
2015-06-04
devicetree: Discriminate device ops scan_bus()
Kyösti Mälkki
2015-06-02
assets: abstract away the firmware assets used for booting
Aaron Durbin
2015-06-02
cbfs: new API and better program loading
Aaron Durbin
2015-05-29
chromeos: always enable timestamps
Stefan Reinauer
2015-05-28
smm: Merge configs SMM_MODULES and SMM_TSEG
Vladimir Serbinenko
2015-05-27
Move TPM code out of chromeos
Vladimir Serbinenko
2015-05-26
acpi: Remove monolithic ACPI
Vladimir Serbinenko
2015-05-23
baytrail: Switch to per-device ACPI
Vladimir Serbinenko
2015-05-21
Remove address from GPLv2 headers
Patrick Georgi
2015-05-13
baytrail: broadwell: correct refcode loading
Aaron Durbin
2015-05-05
3rdparty: move to 3rdparty/blobs
Patrick Georgi
2015-05-05
3rdparty: Move to blobs
Patrick Georgi
2015-05-01
intel: Correct MMIO related ACPI table settings
Dave Frodin
2015-04-30
kbuild: Don't require intel/common changes for every soc
Stefan Reinauer
2015-04-29
kbuild: automatically include SOCs
Stefan Reinauer
2015-04-22
coreboot: common stage cache
Aaron Durbin
2015-04-15
soc/baytrail: Use microcode from the blobs repository
Marc Jones
2015-04-10
baytrail: correct NC pin to GPO pin according to BYT platform design guide
Kane Chen
2015-04-10
baytrail: add code for supporting 2x ddr refresh rate
Kane Chen
2015-04-10
baytrail: fix the coding error on PCIe L1 exit latency
Kevin L Lee
2015-04-10
Baytrail: Prior to PCI scan, wait for LCTL to be active in 50 ms
Kevin Hsieh
2015-04-10
baytrail: Switch from ACPI mode to PCI mode for legacy support
Marc Jones
2015-04-07
baytrail: Change all SoC headers to <soc/headername.h> system
Julius Werner
2015-04-06
baytrail: Fix hdmi audio choppy issue
Kein Yuan
2015-04-06
baytrail: reinitialize spi controller in SMM finalization
Aaron Durbin
2015-04-04
Baytrail: Fix no_dev_behind_port not executed for RP1/2/3.
Kenji Chen
2015-04-03
rmodule: use struct prog while loading rmodules
Aaron Durbin
2015-04-02
baytrail: Change USB3 PLL VCO and iCLK PLL current on BYT-M/D CPU
Kein Yuan
2015-04-02
Baytrail: Change PCIe root disable algorithm
Kenji Chen
2015-04-02
Baytrail: add _PRT to each PCIe root port device
Ted Kuo
2015-04-01
cbfs: correct types used for accessing files
Aaron Durbin
2015-03-30
baytrail: fix HAVE_REFCODE_BLOB build errors
Aaron Durbin
2015-03-30
Update hex values to CBFS binary name types in Makefiles
Martin Roth
2015-03-18
bootstate: use structure pointers for scheduling callbacks
Aaron Durbin
2015-03-10
ACPI: Get S3 resume state from romstage_handoff
Kyösti Mälkki
2015-03-09
coreboot: fix munged license text
Aaron Durbin
2015-02-25
soc/intel/baytrail/Kconfig: Remove explicit `HAVE_MONOTONIC_TIMER`
Paul Menzel
2015-02-16
acpi: Generate valid ACPI processor objects
Timothy Pearson
2015-02-15
x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
Kevin Paul Herbert
2015-01-27
CBMEM: Always use DYNAMIC_CBMEM
Kyösti Mälkki
2015-01-27
CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEM
Kyösti Mälkki
2015-01-27
vboot2: add verstage
Stefan Reinauer
2015-01-16
baytrail: there is a chance that USBPHY_COMPBG is set to 0
Kane Chen
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