summaryrefslogtreecommitdiff
path: root/src/soc/intel/baytrail
AgeCommit message (Expand)Author
2014-12-17x86: Initialize SPI controller explicitly during PCH initDavid Hendricks
2014-12-09spi: Eliminate the spi_cs_activate and spi_cs_deactivate functions.Gabe Black
2014-12-09spi: Remove the spi_set_speed and spi_cs_is_valid functions.Gabe Black
2014-12-08intel/baytrail: Spelling fixesMartin Roth
2014-12-02Replace hlt with halt()Patrick Georgi
2014-11-30Replace hlt() loops with halt()Patrick Georgi
2014-11-25intel: Remove IRQ1 from possible PIRQ assignemnt.Vladimir Serbinenko
2014-11-18baytrail: fix range checkPatrick Georgi
2014-11-13intel: use crosscompiler readelf, instead of globalPatrick Georgi
2014-11-09src: Too many terminators ';;' at end of stmts, stop SkynetEdward O'Callaghan
2014-11-01{cpu,soc}: Use DEVICE_NOOP macro over dummy symbolEdward O'Callaghan
2014-10-28baytrail: Remove unused devicetree fieldsShawn Nematbakhsh
2014-10-28baytrail: gfx: Don't configure hotplug + backlight registersShawn Nematbakhsh
2014-10-28Baytrail/dptf: Always return 0 in TCPU._PPCKein Yuan
2014-10-28baytrail: handle MRC being an ELF fileAaron Durbin
2014-10-28baytrail: Configure MSR for 2-core and 4-core P-state configutationDuncan Laurie
2014-10-28baytrail: move cache-as-ram base address to 0xfe000000Aaron Durbin
2014-10-28baytrail: romstage: Add function to check SW WP status for vbootShawn Nematbakhsh
2014-10-22reg_script: default to n for ARCH_X86Isaac Christensen
2014-10-22cmos: Rename the CMOS related functions.Gabe Black
2014-10-22baytrail: Move HDA verb table to Intel SOC common directoryDuncan Laurie
2014-10-22baytrail: Move MRC cache code to a common directoryDuncan Laurie
2014-10-22baytrail/rambi: S3 support and other updatesKein Yuan
2014-10-19x86 romstage: Move stack just below RAMTOPKyösti Mälkki
2014-10-19haswell baytrail: Enable RELOCATABLE_RAMSTAGEKyösti Mälkki
2014-10-14baytrail: Add padding to the end of device_nvs to match ACPIScott Radcliffe
2014-10-01baytrail: update C0 microcodeShawn Nematbakhsh
2014-09-24baytrail: add 80c microcode for C0 partsAaron Durbin
2014-09-19baytrail/rambi: spi, charger, and audio updatesAaron Durbin
2014-09-18rambi/baytrail: ACPI, GPIO, audio, misc updatesShawn Nematbakhsh
2014-08-28soc/intel/baytrail/Kconfig: Remove empty line at top filePaul Menzel
2014-08-15Move baytrail-specific config to baytrail.Vladimir Serbinenko
2014-07-23src/.../Kconfig: various small fixes to textsDaniele Forsi
2014-07-17soc,ASL: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
2014-07-14SPI: Split writes using spi_crop_chunk()Kyösti Mälkki
2014-07-08soc: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
2014-07-05spi: Change spi_xfer to work in units of bytes instead of bits.Gabe Black
2014-07-05spi: Remove unused parameters from spi_flash_probe and setup_spi_slave.Gabe Black
2014-06-21intel boards: Use acpi_is_wakeup_s3()Kyösti Mälkki
2014-06-18ACPI: Remove CBMEM TOC from GNVSKyösti Mälkki
2014-05-17build: separate CPPFLAGS from CFLAGSPatrick Georgi
2014-05-17build: CPPFLAGS is more common than INCLUDESPatrick Georgi
2014-05-15baytrail: Add SOC thermal settingsDuncan Laurie
2014-05-15baytrail: Enable PCIe common clock and ASPMDuncan Laurie
2014-05-15baytrail: enable graphics turboAaron Durbin
2014-05-15baytrail: use CPU_INTEL_TURBO_NOT_PACKAGE_SCOPEDAaron Durbin
2014-05-15baytrail: Add ACPI Device for XHCIDuncan Laurie
2014-05-15baytrail: nvm: use proper types for checking eraseAaron Durbin
2014-05-15baytrail: mrc_cache: check region erased before erasingAaron Durbin
2014-05-13baytrail: add C0 microcode updateAaron Durbin
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 16:44:47 +0000