coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-03-23	soc/intel/braswell: Clean up	Angel Pons
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2020-03-09	soc/intel/braswell/chip.h: Include smbios.h for Type9 Entries	Michał Żygowski
2019-10-03	soc/intel/braswell/chip.h: Add IGD_MEMSIZE_xxMB	Frans Hendriks
2019-08-20	devicetree: Remove duplicate chip_ops declarations	Kyösti Mälkki
2019-05-07	soc/intel/bsw: Move memory init values into `romstage.h`	Nico Huber
2019-05-03	soc/intel/braswell: add default option to use public FSP	Matt DeVillier
2019-04-04	soc/intel/braswell: Correct serial IRQ support	Frans Hendriks
2017-09-08	soc/intel/braswell: add USB2 PHY PERPORTRXISET UPD	Kevin Chiu
2017-09-08	soc/intel/braswell: Add I2C clock config options	Divagar Mohandass
2017-03-17	soc/intel/braswell: Fix most of the issues detected by checkpatch	Lee Leahy
2017-03-17	soc/intel/braswell: Fix spacing issues detected by checkpatch	Lee Leahy
2016-01-28	soc/braswell: Add interface to program USB2_COMPBG register	shkim
2016-01-28	Strago: Enable CA Mirror	Shobhit Srivastava
2016-01-28	soc/braswell: Disable SD card detect simulation in FSP	Divya Sasidharan
2016-01-28	soc/braswell: Fix DSP clock	fdurairx
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-10-11	Braswell: Modify CB to accomodate new FSPv83	Subrata Banik
2015-09-10	fsp1_1: provide binding to UEFI version	Aaron Durbin
2015-07-29	intel/braswell: fix build	Jenny TC
2015-07-29	BCRD2: Enable PMIC SVID config	Jenny TC
2015-07-06	Braswell: Update to end of June.	Lee Leahy
2015-06-25	Braswell: Add Braswell SOC support	Lee Leahy
2015-05-28	Remove address from GPLv2 headers	Patrick Georgi
2015-05-23	Braswell: Use Baytrail as Comparison Base	Lee Leahy