coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-09-21	src/soc/intel: Drop unneeded empty lines	Elyes HAOUAS
2020-07-09	soc/intel/braswell: Drop some BIOS_SPEW printk's	Angel Pons
2020-06-30	ACPI: Drop typedef global_nvs_t	Kyösti Mälkki
2020-06-24	ACPI: Replace uses of CBMEM_ID_ACPI_GNVS	Kyösti Mälkki
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-01	soc/intel/braswell: Fix 16-bit read/write PCI_COMMAND register	Elyes HAOUAS
2020-04-06	soc/intel/braswell: Use SPDX for GPL-2.0-only files	Angel Pons
2020-04-05	Drop explicit NULL initializations from `device_operations`	Elyes HAOUAS
2020-03-23	soc/intel/braswell: Clean up	Angel Pons
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2019-07-18	soc/intel: Use config_of()	Kyösti Mälkki
2019-03-04	device/mmio.h: Add include file for MMIO ops	Kyösti Mälkki
2019-03-01	device/pci: Fix PCI accessor headers	Kyösti Mälkki
2018-10-23	src: Remove unneeded whitespace	Elyes HAOUAS
2018-06-04	soc/intel/braswell: Get rid of device_t	Elyes HAOUAS
2018-03-08	soc/intel/braswell: add resource allocation for LPE BAR1	Matt DeVillier
2018-03-06	soc/intel/braswell: increase LPEA fw allocation to 2MiB	Matt DeVillier
2017-03-17	soc/intel/braswell: Fix most of the issues detected by checkpatch	Lee Leahy
2017-03-17	soc/intel/braswell: Add int to unsigned	Lee Leahy
2016-01-28	soc/braswell: Fix DSP clock	fdurairx
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-06-25	Braswell: Add Braswell SOC support	Lee Leahy
2015-05-28	Remove address from GPLv2 headers	Patrick Georgi
2015-05-23	Braswell: Use Baytrail as Comparison Base	Lee Leahy