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path: root/src/soc/intel/braswell/memmap.c
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2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-27FSP 1.1: Move common FSP codeLee Leahy
Move the FSP common code from the src/soc/intel/common directory into the src/drivers/intel/fsp1_1 directory. Rename the Kconfig values associated with this common code. BRANCH=none BUG=None TEST=Build and run on kunimitsu Change-Id: If1ca613b5010424c797e047c2258760ac3724a5a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e8228cb2a12df1cc06646071fafe10e50bf01440 Original-Change-Id: I4ea84ea4e3e96ae0cfdbbaeb1316caee83359293 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/306350 Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12156 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2015-08-14intel/common: fix stage_cache_external_region()Aaron Durbin
The stage_cache_external_region() calculation is actually dependennt on the properties of the chipset. The reason is that certain regions within the SMRAM are used for chipset-specific features. Therefore, provide an API for abstracting the querying of subregions within the SMRAM. The 3 subregions introduced are: SMM_SUBREGION_HANDLER - SMM handler area SMM_SUBREGION_CACHE - SMM cache region SMM_SUBREGION_CHIPSET - Chipset specific area. The subregions can be queried using the newly added smm_subregion() function. Now stage_cache_external_region() uses smm_subregion() to query the external stage cache in SMRAM, and this patch also eliminates 2 separate implementations of stage_cache_external_region() between romstage and ramstage. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, resumed on glados. Original-Change-Id: Id669326ba9647117193aa604038b38b364ff0f82 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290833 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Idb1a75d93c9b87053a7dedb82e85afc7df6334e0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11197 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-21intel fsp: remove CHIPSET_RESERVED_MEM_BYTESAaron Durbin
FSP 1.1 platforms should be conforming to the spec. In order to ensure following specification remove the crutch that allows FSP to no conform. BUG=chrome-os-partner:41961 BRANCH=None TEST=Built. Change-Id: I28b876773a3b6f07223d60a5133129d8f2c75bf6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c3fe08c5af41867782e422f27b0aed1b762ff34a Original-Change-Id: Ib97027a35cdb914aca1eec0eeb225a55f51a4b4b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/285187 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/10993 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-25Braswell: Add Braswell SOC supportLee Leahy
Add the files to support the Braswell SOC. BRANCH=none BUG=None TEST=Build for a Braswell platform Change-Id: I968da68733e57647d0a08e4040ff0378b4d59004 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10051 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-28Remove address from GPLv2 headersPatrick Georgi
Follow up for commit b890a12, some contributions brought back a number of FSF addresses, so get rid of them again. Change-Id: I0ac0c957738ce512deb0ed82b2219ef90d96d46b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10322 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-05-23Braswell: Use Baytrail as Comparison BaseLee Leahy
Add baytrail source for comparison with Braswell. BRANCH=none BUG=None TEST=None Change-Id: I5170addf41676d95a3daf070a32bcee085f8156d Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10117 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>