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coreboot
2560p
820g2
autoport-hsw
broadwell_refcode
e6230
e7240_bdw
haswell-mrc
hp820g1
hp9480m
mec1322
Some coreboot project code with my work
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src
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soc
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intel
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braswell
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ramstage.c
Age
Commit message (
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Author
2020-03-23
soc/intel/braswell: Clean up
Angel Pons
2020-03-18
soc: Remove copyright notices
Patrick Georgi
2019-12-19
src/soc/intel: Remove unused <stdlib.h>
Elyes HAOUAS
2019-03-20
src: Use 'include <string.h>' when appropriate
Elyes HAOUAS
2019-01-06
device: Use pcidev_on_root()
Kyösti Mälkki
2018-10-11
src: Move common IA-32 MSRs to <cpu/x86/msr.h>
Elyes HAOUAS
2018-09-21
soc/intel/braswell/ramstage.c: Add SoC stepping D-1 support
Frans Hendriks
2018-07-09
src/soc: Use "foo *bar" instead of "foo* bar"
Elyes HAOUAS
2018-06-04
soc/intel/braswell: Get rid of device_t
Elyes HAOUAS
2016-07-15
soc/intel/braswell: don't duplicate setting ACPI sleep state
Aaron Durbin
2016-01-28
soc/braswell: Set max frequency to be turbo frequency
Hannah Williams
2016-01-14
soc/braswell: Fix P-state table
Subrata Banik
2015-10-31
tree: drop last paragraph of GPL copyright header
Patrick Georgi
2015-10-27
FSP 1.1: Move common FSP code
Lee Leahy
2015-09-17
braswell: Switch to using common ACPI _SWS code
Duncan Laurie
2015-09-10
fsp1_1: provide binding to UEFI version
Aaron Durbin
2015-06-25
Braswell: Add Braswell SOC support
Lee Leahy
2015-05-28
Remove address from GPLv2 headers
Patrick Georgi
2015-05-23
Braswell: Use Baytrail as Comparison Base
Lee Leahy