coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-01	soc/intel/braswell: Fix 16-bit read/write PCI_COMMAND register	Elyes HAOUAS
2020-04-06	soc/intel/braswell: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-23	soc/intel/braswell: Clean up	Angel Pons
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2020-03-03	soc/braswell: hook up smmstore	Matt DeVillier
2019-12-19	src/soc/intel: Remove unused <stdlib.h>	Elyes HAOUAS
2019-11-29	soc/intel/braswell: Don't reinitialize SPI after lockdown	Arthur Heymans
2019-11-09	ELOG: Introduce elog_gsmi variants	Kyösti Mälkki
2019-08-13	cpu/x86: Separate save_state struct headers	Kyösti Mälkki
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
2019-03-04	device/mmio.h: Add include file for MMIO ops	Kyösti Mälkki
2019-03-01	device/pci: Fix PCI accessor headers	Kyösti Mälkki
2018-12-05	elog: make elog's SMM handler code follow everything else	Patrick Georgi
2018-06-14	src: Use of device_t is deprecated	Elyes HAOUAS
2016-07-15	soc/intel/braswell: use common Intel ACPI hardware definitions	Aaron Durbin
2016-01-27	soc/braswell: Fix leakage on V1P8S rail	Shobhit Srivastava
2016-01-07	Correct some common spelling mistakes	Martin Roth
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-09-08	braswell: Tristate CFIO 139 and CFIO 140	Ravi Sarawadi
2015-06-25	Braswell: Add Braswell SOC support	Lee Leahy
2015-05-28	Remove address from GPLv2 headers	Patrick Georgi
2015-05-23	Braswell: Use Baytrail as Comparison Base	Lee Leahy