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coreboot
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Some coreboot project code with my work
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intel
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spi.c
Age
Commit message (
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Author
2017-03-17
soc/intel/braswell: Fix most of the issues detected by checkpatch
Lee Leahy
2017-03-17
soc/intel/braswell: Add int to unsigned
Lee Leahy
2016-12-23
spi: Get rid of SPI_ATOMIC_SEQUENCING
Furquan Shaikh
2016-12-05
spi: Define and use spi_ctrlr structure
Furquan Shaikh
2016-12-05
spi: Pass pointer to spi_slave structure in spi_setup_slave
Furquan Shaikh
2016-12-05
spi: Fix parameter types for spi functions
Furquan Shaikh
2016-12-04
spi_flash: Move spi flash opcodes to spi_flash.h
Furquan Shaikh
2016-11-22
spi: Clean up SPI flash driver interface
Furquan Shaikh
2015-10-31
tree: drop last paragraph of GPL copyright header
Patrick Georgi
2015-09-07
Drop "See file CREDITS..." comment
Stefan Reinauer
2015-09-04
bootstate: remove need for #ifdef ENV_RAMSTAGE
Aaron Durbin
2015-07-06
Braswell: Update to end of June.
Lee Leahy
2015-06-25
Braswell: Add Braswell SOC support
Lee Leahy
2015-05-28
Remove address from GPLv2 headers
Patrick Georgi
2015-05-23
Braswell: Use Baytrail as Comparison Base
Lee Leahy