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path: root/src/soc/intel/braswell
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2019-10-08device: Use scan_static_bus() over scan_lpc_bus()Nico Huber
Devices behind LPC can expose more buses (e.g. I2C on a super-i/o). So we should scan buses on LPC devices, too. Change-Id: I0eb005e41b9168fffc344ee8e666d43b605a30ba Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29474 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-03soc/intel/braswell/chip.h: Add IGD_MEMSIZE_xxMBFrans Hendriks
Add defines to have some more readable code for devcietree.cb. BUG=N/A TEST=4K HDMI monitor and LCD working fine on Facebook FBG-1701 Change-Id: Ifc1a7657a528d1fc570dd16df66b078e37e014cb Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-02intel/pci_devs: Regroup PCI xx_DEVID entriesKyösti Mälkki
Change-Id: I953e9a7746232b4c40deca55eb6cb3bd7af91496 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-15src/soc: Remove unused include <device/pci_ops.h>Elyes HAOUAS
Change-Id: I80c92f744fb9a6c3788b8b9ba779deef76e58943 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33530 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28intel/braswell: Use smm_subregion()Kyösti Mälkki
Change-Id: I4af661f68c158cbed591fe017d4bc25239bddd37 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34758 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26lib/bootblock: Add simplified entry with basetimeKyösti Mälkki
This allows for minor optimization as num_timestamps becomes a constant zero for a function with local scope. The loop with calls to timestamp_add() gets removed from bootblock. Change-Id: Id230075c0e76fe377b6ea8c8ddf8318e07d29b91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-26Split MAYBE_STATIC to _BSS and _NONZERO variantsKyösti Mälkki
These are required to cover the absensce of .data and .bss sections in some programs, most notably ARCH_X86 in execute-in-place with cache-as-ram. Change-Id: I80485ebac94b88c5864a949b17ad1dccdfda6a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-20src: Remove variable length arraysJacob Garber
Variable length arrays were a feature added in C99 that allows the length of an array to be determined at runtime. Eg. int sum(size_t n) { int arr[n]; ... } This adds a small amount of runtime overhead, but is also very dangerous, since it allows use of an unlimited amount of stack memory, potentially leading to stack overflow. This is only worsened in coreboot, which often has very little stack space to begin with. Citing concerns like this, all instances of VLA's were recently removed from the Linux kernel. In the immortal words of Linus Torvalds [0], AND USING VLA'S IS ACTIVELY STUPID! It generates much more code, and much _slower_ code (and more fragile code), than just using a fixed key size would have done. [...] Anyway, some of these are definitely easy to just fix, and using VLA's is actively bad not just for security worries, but simply because VLA's are a really horribly bad idea in general in the kernel. This patch follows suit and zaps all VLA's in coreboot. Some of the existing VLA's are accidental ones, and all but one can be replaced with small fixed-size buffers. The single tricky exception is in the SPI controller interface, which will require a rewrite of old drivers to remove [1]. [0] https://lkml.org/lkml/2018/3/7/621 [1] https://ticket.coreboot.org/issues/217 Change-Id: I7d9d1ddadbf1cee5f695165bbe3f0effb7bd32b9 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-20devicetree: Remove duplicate chip_ops declarationsKyösti Mälkki
These are only referenced inside auto-generated static.c files, and util/sconfig also generates the declarations automatically from source file pathnames. Change-Id: Id324790755095c36fbeb73a4d8f9d01cdf6409cb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34979 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15soc/intel: Rename some SMM support functionsKyösti Mälkki
Rename southbridge_smm_X to smm_southbridge_X. Rename most southcluster_smm_X to smm_southbridge_X. Change-Id: I4f6f9207ba32cf51d75b9ca9230e38310a33a311 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34856 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15soc/intel: Drop spurious includesKyösti Mälkki
Change-Id: I2fff107e38abdd34f2d80d4d258be4c429d371e7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-15cpu/x86/smm: Define single smm_subregion()Kyösti Mälkki
At the moment we only have two splitting of TSEG, one with and one without IED. They can all use same implementation. Make configuration problems of TSEG region assertion failures. Rename file from stage_cache.c to tseg_region.c to reflect it's purpose. Change-Id: I9daf0dec8fbaaa1f4e6004ea034869f43412d7d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34776 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Guckian Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-13cpu/x86: Separate save_state struct headersKyösti Mälkki
Any platform should need just one of these. Change-Id: Ia0ff8eff152cbd3d82e8b372ec662d3737078d35 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34820 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-08soc/intel/{APL, BSW, SKL}: Remove unused CPU_ADDR_BITS kconfigSubrata Banik
This patch removes CONFIG_CPU_ADDR_BITS kconfig from soc/intel/<soc>/Kconfig as not getting used anymore. Change-Id: Ie7fa386c9c0aae19da1fbd09407494d9812247a4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34768 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-08arch/x86: Handle smm_subregion() failureKyösti Mälkki
The callers don't necessarily check return value of function. Make sure the parameters are not left uninitialised in that case. Change-Id: Ic02db2d35b2ec88506320e7df609940de4aef005 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34708 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-08arch/x86: Change smm_subregion() prototypeKyösti Mälkki
Do this to avoid some amount of explicit typecasting that would be required otherwise. Change-Id: I5bc2c3c1dd579f7c6c3d3354c0691e4ba3c778e1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-08lib/stage_cache: Refactor Kconfig optionsKyösti Mälkki
Add explicit CBMEM_STAGE_CACHE option. Rename CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM to TSEG_STAGE_CACHE. Platforms with SMM_TSEG=y always need to implement stage_cache_external_region(). It is allowed to return with a region of size 0 to effectively disable the cache. There are no provisions in Kconfig to degrade from TSEG_STAGE_CACHE to CBMEM_STAGE_CACHE. As a security measure CBMEM_STAGE_CACHE default is changed to disabled. AGESA platforms without TSEG will experience slower S3 resume speed unless they explicitly select the option. Change-Id: Ibbdc701ea85b5a3208ca4e98c428b05b6d4e5340 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-07intel/braswell: Drop config IED_REGION_SIZEKyösti Mälkki
Platform does not set up IED. Change-Id: Ied72888c6406b59332bc3d68eccb50bf1eab3419 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-07cpu/x86/smm: Promote smm_subregion()Kyösti Mälkki
No need to limit these declarations to FSP. Both PARALLEL_MP_INIT smm_relocate() and TSEG_STAGE_CACHE can be built on top of this. Change-Id: I7b0b9b8c8bee03aabe251c50c47dc42f6596e169 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-07soc/intel: Obsolete mmap_region_granularity()Kyösti Mälkki
Change-Id: I471598d3ce61b70e35adba3bd983f5d823ba3816 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-07-18soc/intel: Use config_of()Kyösti Mälkki
Change-Id: I0727a6b327410197cf32f598d1312737744386b3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Guckian
2019-07-10soc/intel/braswell/acpi/lpc.asl: Allocate used ROM size onlyFrans Hendriks
Fixed ROM area is allocated. Reduce the ROM size using CONFIG_COREBOOT_ROMSIZE. BUG=N/A TEST=Facebook FBG-1701 booting Embedded Linux Change-Id: I7a47bf2600f546271c5a65641d29f868ff2748bf Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-09arch/x86: Flip HAVE_MONOTONIC_TIMER defaultKyösti Mälkki
Change-Id: Id56139a3d0840684b13179821a77bc8ae28e05ae Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-09cpu/x86: Flip SMM_TSEG defaultKyösti Mälkki
This is only a qualifier between TSEG and ASEG. Change-Id: I8051df92d9014e3574f6e7d5b6f1d6677fe77c82 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-20soc/intel/braswell/smbus.c: Add support for i2c mode block writeFrans Hendriks
Intel Braswell supports i2c block write using SMBus controller. smbus_i2c_block_write() is added to configure SMBus controller in i2c mode before calling do_i2c_block_write(). Add smbus.c to ramstage. BUG=N/A TEST=Verify LCD display is working on Facebook FBG-1701 Change-Id: I50c1a03f624b3ab3b987d4f3b1d15dac4374e48a Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-06-12{drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK supportFrans Hendriks
No C_ENVIRONMENT_BOOTBLOCK support for Braswell is available. Enable support and add required files for the Braswell Bootblock in C. The next changes are made support C_ENVIRONMENT_BOOTBLOCK: - Add car_stage_entry() function bootblock-c_entry() functions. - Specify config DCACHE_BSP_STACK_SIZE and C_ENV_BOOTBLOCK_SIZE. - Add bootblock_c_entry(). - Move init from car_soc_XXX_console_init() to bootblock_soc_XXX_Init() Removed the unused cache_as_ram_main() and weak car_XXX_XXX_console_init() BUG=NA TEST=Booting Embedded Linux on Facebook FBG-1701 Building Google Banos Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-06-04soc/intel/braswell: Use common cpu/intel/car codeArthur Heymans
The code in cpu/intel/car/romstage.c Does most of the things like setting up timestamps, stack guards, entering postcar. A functional difference is that the FSP header is searched for twice instead of passed from the CAR entry to the C code. When using C_ENVIRONMENT_BOOTBLOCK this needs to be done anyway (or a special linker symbol kept across multiple stages is needed, which is likely not worth the speedup). Change-Id: I0f03e5a808f00157fdd807b104417a54e4bde7b2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-29soc/intel/braswell/acpi/globalnvs.asl: Remove redundant use of OffsetFrans Hendriks
ASL compiler reports twice warning 'unnecessary/redundant use of Offfset operator'. Remove redundant offsets. BUG=N/A TEST=Facebook FBG-1701 booting Embedded Linux Change-Id: I16705b9392b17c50d3988012406e03de393cbcd2 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-05-29sb/intel/*: Delete early_spiPatrick Rudolph
The file and all of it's functions are unused. Drop the dead code. Change-Id: Iaddd7a688d431d40f38293939e084d19b286aed4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: David Guckian Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-05-29soc/intel/braswell: Don't use CAR_GLOBALArthur Heymans
Now that this soc supports NO_CAR_GLOBAL_MIGRATION CAR_GLOBAL and car_get/set_x are not needed anymore. Change-Id: Ia7fa97135a4b376ac0bd8b30093a77614cc2cf55 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-22soc/{baytrail/braswell/broadwell}: fix flashconsole on platformMatt DeVillier
Enabling flashconsole on these platforms fails to build due to spi.c not being compiled in prior to ramstage. Include in early stages (bootblock/romstage/postcar) as needed to enable flashconsole support. Early inclusion of monotonic_timer.c is needed for Broadwell as well. Change-Id: Idae0578ca92939246021bb85e34b0dcbd41df3b5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-21soc/intel/fsp1.1: Implement postcar stageArthur Heymans
This moves FSP1.1 to use postcar stage to tear down CAR. On platforms with USE_GENERIC_FSP_CAR_INC the FSP header is found during the postcar stage so there is no need to push to save it in CAR global variables. On FSP1.1 platforms with an open source CAR implementation (Skylake, even though it still runs the FSP-T), the soc/intel/common/blocks/cpu/car/exit_car.S code tears down CAR. This also uses common functions to set up the MTRR to use after CAR is torn down. Test: build/boot on google/celes (BSW) and google/chell (SKL) Change-Id: I2330993842aae9c1365230f0c6bd8a2449dc73a5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-05-20soc/intel/braswell/pmutil.c: Use GEN_PMCON1 for RTC statusFrans Hendriks
cbmem_find is not available in every stage. Remove usage of cbmem_find() and use GEN_PMCON1 always. BUG=NA TEST=Booting Embedded Linux on Facebook FBG-1701 Change-Id: Id97d57864b3e241e8f046d9b1caebdce199a46b1 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-13soc/intel/braswell: Remove unused include <timestamp.h>Elyes HAOUAS
Change-Id: Ied645a583f78bc47c8358240acd639132fd499db Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2019-05-13soc/intel/braswell: Add tsc_freq.c and pmutil.c in verstageFrans Hendriks
Systems with C_EVIRONMENT_BOOTBLOCK and VBOOT enabled requires functions tsc_freq_mhz(), vbnv_cmos_failed() and vboot_platform_is_resuming() in verstage. Add tsc_freq.c and pmutil.c to verstage. BUG=NA TEST=Booting Embedded Linux on Facebook FBG-1701 + Building Google Banon Change-Id: Ia509eda6bf415aaa63be71013249493aa472289d Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-10soc/intel/braswell/smbus: Enable early SMBus in romstageMichał Żygowski
Enable early SMBus support compatible with SPD library using Intel SB common SMBus API. TEST=boot Protectli FW2B with new FSP, MemoryInit should pass without errors Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I92a2c5a6d0b38e5658cfdc017041f12717dabdd5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-07intel/fsp1_1: Drop remnants of `pei_data`Nico Huber
`pei_data` was a struct with blob parameters from pre-FSP times. Somehow, it sneaked into upstream FSP1.1 support (probably because early board ports were written for a different blob). When added upstream, its usage was already perverted. It was declared at SoC level but mostly used to pass mainboard data from mainboard code to itself and FSP data from FSP code to itself. Now that no board/ SoC code uses it anymore, we can finally drop it. Change-Id: Ib0bc402703188539cf2254bdc395cca9dd32d863 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-07soc/intel/bsw: Move memory init values into `romstage.h`Nico Huber
`chip.h` is usually used as devicetree interface. Change-Id: Ied30927d68927b86758a84ccf3f5fbd8cce632f1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32592 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-07intel/fsp1_1: Move MRC cache pointers into `romstage_params`Nico Huber
These are part of a common concept and not SoC specific. Change-Id: I9cb218d7825bd06a138f7f5d9e2b68e86077a3ec Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-05-07intel/fsp1_1: Drop `boot_mode` from `pei_data`Nico Huber
It was only used locally. Change-Id: Iaaad760e8ceca62655f5448c30846cf11959e8e1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-05-06soc/intel/braswell/Makefile.inc: Remove commented-out lineFrans Hendriks
cpu_microcode_bins is commented out. Remove this line. BUG=NA TEST=Portwell PQ7-M107 Change-Id: Ic398d232bea84a765fce940ef876916a873e561f Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32510 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-03{soc, southbridge} : Correct typo in commentFrans Hendriks
BUG=N/A TEST=N/A Change-Id: I1b207e0b77bac8860ba7501378297c1f3604141c Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32453 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-03soc/intel/braswell: add default option to use public FSPMatt DeVillier
The current Braswell FSP 1.1 header in vendorcode/intel, for which there is no publicly available FSP binary, contains silicon init UPDs which are not found in the publicly available header/binary in the FSP Github repo. This prevents new boards from being added which use the public Braswell FSP header/binary. To resolve this, move the UPDs not found in the public header from the soc's chip.c to ramstage.c for the boards which use them. Add a Kconfig option to use the current non-public FSP header and select it for boards which need it (google/cyan variants); set the public FSP option as the default. Use the Kconfig option to set FSP_HEADER_PATH to ensure the correct header is used. Test: build google/cyan and intel/strago using non-public and public FSP header/binaries respectively. Change-Id: I43cf18b98c844175a87b61fdbe4b0b24484e5702 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-30vboot: refactor OPROM codeJoel Kitching
The name OPROM is somewhat inaccurate, since other steps to bring up display and graphics are needed depending on mainboard/SoC. This patch cleans up OPROM code nomenclature, and works towards the goal of deprecating vboot1: * Rename CONFIG_VBOOT_OPROM_MATTERS to CONFIG_VBOOT_MUST_REQUEST_DISPLAY and clarify Kconfig description * Remove function vboot_handoff_skip_display_init * Remove use of the VbInit oflag VB_INIT_OUT_ENABLE_DISPLAY * Add |flags| field to vboot_working_data struct * Create VBOOT_FLAG_DISPLAY_REQUESTED and set in vboot_handoff BUG=b:124141368, b:124192753, chromium:948529 TEST=make clean && make test-abuild TEST=build and flash eve device; attempt loading dev/rec modes BRANCH=none Change-Id: Idf111a533c3953448b4b9084885a9a65a2432a8b Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-29soc/intel/braswell: Move LPE ACPI code to mainboardFrans Hendriks
The ACPI code of LPE device is included regardless of the availability of the LPE controller. Linux remains requesting the status of device LPEA even if this device is disabled. Include ACPI LPE controller code at Braswell mainboards with LPE enabled. BUG=N/A TEST=Linux 4.17+ on Portwell PQ7-M107 Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-04-26soc/{amd,intel}/chip: Use local include for chip.hElyes HAOUAS
Change-Id: Ic1fcbf4b54b7d0b5cda04ca9f7fc145050c867b8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-23soc/intel/braswell/acpi/lpss.asl: Remove SPI1 and PWM asl codeFrans Hendriks
Linux remains using SPI1 and PWM ASL even if these devices are disabled. SPI1 and PWM are disabled by Intel FSP. Remove ASL code. BUG=N/A TEST=Boot Ubuntu on Intel CherryHill CRB Change-Id: Iec2ca7520081d00bf7a53d58ee054aa6f23e5606 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-04-08{src,util}: Correct typo in comment and debug stringFrans Hendriks
Correct typo in comment and debug string. BUG=N/A TEST=build Change-Id: I0362bb8d7c883e7fcbc6a2fc2f9918251f0d8d6e Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29321 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-06src: Use include <delay.h> when appropriateElyes HAOUAS
Change-Id: I23bc0191ca8fcd88364e5c08be7c90195019e399 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian
2019-04-04soc/intel/braswell: Correct serial IRQ supportFrans Hendriks
Serial IRQ was configured in quiet mode, but not enabled. Enable serial IRQ and use 'enum seriirq_mode' as a devicetree option. Function sc_enable_serial_irqs() is added to enabled serial IRQs. enable_serirq_quiet_mode() is renamed to sc_set_serial_irqs_mode(). This function use the 'serirq_mode' to set the mode. The call to this function is moved from finalize to init having serial IRQs enable in early stage. Serial IRQs must be enabled in continuous mode for at least one frame before switching into quiet mode. BUG=N/A TEST=Portwell PQ7-M107 Change-Id: I7844cad69dc0563fa6109d779d0afb7c2edd7245 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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