summaryrefslogtreecommitdiff
path: root/src/soc/intel/broadwell/pcie.c
AgeCommit message (Expand)Author
2015-04-10broadwell: Set PCIe replay timeout to 0xDDuncan Laurie
2015-04-10broadwell: Skip steps when disabling PCIe portDuncan Laurie
2015-04-10broadwell: Fix PCIe ports programming sequences to enable HSIOPCWenkai Du
2015-04-10Broadwell: Synchronization with FRC for Root Port Power ManagementKenji Chen
2015-04-07broadwell: Change all SoC headers to <soc/headername.h> systemJulius Werner
2015-04-04Broadwell: Fix PCIe L1 Sub-State capability ID not filled.Kenji Chen
2015-04-02Broadwell: Select PCIE_L1_SUB_STATE and apply Broadwell settings.Kenji Chen
2015-04-02Broadwell: Synchronize for power management with FRCKenji Chen
2015-04-02Broadwell: Synchronize RO, Link Arbiter, and OBFF with FRCKenji Chen
2015-04-02Broadwell: Revise programming flow for write-once registersKenji Chen
2015-04-02broadwell: Configure IOSF Port and Grant CountKenji Chen
2015-04-02broadwell: Update PCIe configuration to follow BWGKane Chen
2015-03-27broadwell: Fix some errors in selftestKane Chen
2015-03-27broadwell: Apply pcie updates from 2.1.0 ref codeKane Chen
2015-03-27broadwell: Misc updates from 2.1.0 ref codeDuncan Laurie
2014-12-08intel/broadwell: Spelling fixesMartin Roth
2014-10-22broadwell: add new intel SOCDuncan Laurie
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-15 04:22:10 +0000