coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2016-07-31	intel/broadwell: fix typo	Patrick Georgi
2015-12-20	soc/intel/broadwell: Init var before use, only use when needed	Martin Roth
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-04-10	broadwell: Set PCIe replay timeout to 0xD	Duncan Laurie
2015-04-10	broadwell: Skip steps when disabling PCIe port	Duncan Laurie
2015-04-10	broadwell: Fix PCIe ports programming sequences to enable HSIOPC	Wenkai Du
2015-04-10	Broadwell: Synchronization with FRC for Root Port Power Management	Kenji Chen
2015-04-07	broadwell: Change all SoC headers to <soc/headername.h> system	Julius Werner
2015-04-04	Broadwell: Fix PCIe L1 Sub-State capability ID not filled.	Kenji Chen
2015-04-02	Broadwell: Select PCIE_L1_SUB_STATE and apply Broadwell settings.	Kenji Chen
2015-04-02	Broadwell: Synchronize for power management with FRC	Kenji Chen
2015-04-02	Broadwell: Synchronize RO, Link Arbiter, and OBFF with FRC	Kenji Chen
2015-04-02	Broadwell: Revise programming flow for write-once registers	Kenji Chen
2015-04-02	broadwell: Configure IOSF Port and Grant Count	Kenji Chen
2015-04-02	broadwell: Update PCIe configuration to follow BWG	Kane Chen
2015-03-27	broadwell: Fix some errors in selftest	Kane Chen
2015-03-27	broadwell: Apply pcie updates from 2.1.0 ref code	Kane Chen
2015-03-27	broadwell: Misc updates from 2.1.0 ref code	Duncan Laurie
2014-12-08	intel/broadwell: Spelling fixes	Martin Roth
2014-10-22	broadwell: add new intel SOC	Duncan Laurie