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path: root/src/soc/intel/broadwell/sata.c
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2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-04-13broadwell: Fix incorrect SATA port map maskWenkai Du
WPT-LP has 4 SATA ports. Current code assumes 6 SATA ports and as a result, some reserved bits are written with 1. No specific issue has been observed so far. BUG=None BRANCH=None TEST=Verify SATA PCI configure space dump on Auron Change-Id: I737719b3d5cd788158cd5b6991405ba098be4078 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 2b55587a74ac5d45354dc123937b562290468855 Original-Change-Id: I9c53ac86e2bf72901647bd2cfa48ac0ce31abea0 Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/233661 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9479 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Update SATA Gen3 TX adjustment registersDuncan Laurie
The registers that were used here are for CPT/PPT and not for HSW/BDW chips. Update this to update just the Gen3 TX Output Voltage Downscale Amplitude Adjustment field in the SATA ECR T88. BUG=chrome-os-partner:28234 BRANCH=samus,auron TEST=build and boot on samus Change-Id: I94b702dc4a3c98678ba048ff9cfa4a85cc5b1eed Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 4c5816cc647b84266751e8a591eb85d7735fee12 Original-Change-Id: I98ec9678938a6675828721d5b57683077f555d21 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/238800 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9484 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-07broadwell: Change all SoC headers to <soc/headername.h> systemJulius Werner
This patch aligns broadwell to the new SoC header include scheme. BUG=None TEST=Tested with whole series. Compiled Auron and Samus. Change-Id: I0cb6aa3d17ce28890e586be1c2c7ad16d91dd925 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 23bcaa8110c4b63999c6ebf370045e9bef87ce6e Original-Change-Id: I613ec0e2b970c75d1f8f7d9bb454bcf11abc78f0 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224507 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9364 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Fix some errors in selftestKane Chen
1. Fixed some errors in selftest compare to reference. 2. Some WA steps for xhci in sleep trap is only for lpt. BUG=chrome-os-partner:28234 TEST=compile ok, run selftest on auron to verify boot to OS BRANCH=None Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Change-Id: Iaccb087581d5f51453614246bf80132fcb414131 Original-Reviewed-on: https://chromium-review.googlesource.com/215646 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Kane Chen <kane.chen@intel.com> Original-Tested-by: Kane Chen <kane.chen@intel.com> (cherry picked from commit 97761b4ad3073fff89aabce3ef4f763383ca5cad) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I2b1d5be4f8a13eb00009a36a199520cd35a67abf Reviewed-on: http://review.coreboot.org/8971 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27broadwell: Changes from 2.2.0 ref codeDuncan Laurie
- The SATA CAP register setup was moved outside the refcode blob we run so it needs to be set up by coreboot again... - Slight tweak to fast ramp voltage for broadwell CPU BUG=chrome-os-partner:25491 BRANCH=None TEST=Build and boot on samus Original-Change-Id: I7bdc0811ad8f28ab0912972036dca59d229b0173 Original-CSigned-off-by: Duncan Laurie <dlaurie@chromium.org> Original-CReviewed-on: https://chromium-review.googlesource.com/214024 Original-CReviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 5d166a0c4d206eaa885ecebaa0c3cefefdc59280) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id58d3bee5e713139edf6e8fda8cdf4c48ba95bd1 Reviewed-on: http://review.coreboot.org/8964 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: sata updates from 2.1.0 ref codeKane Chen
fixed a coding error and sync sata configuration with ref code BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus verify registers between samus and crb Original-Change-Id: I09dd80a9772ac82b841363a540c9b7a8689e04a9 Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/213137 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit 0fbb59e3c5117a513ef19117560bb41dfe8c0d71) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I99a389b06f4ec077c298100ca878c68ef69debfa Reviewed-on: http://review.coreboot.org/8959 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Fix devslp enable to use correct registerDuncan Laurie
This was a merge error when I was pulling in some of the code into this file I put it after the read of CAP2 but before it is modified and written back. In the end the DEVSLP bits are getting set/cleared that need to but the other bits in the register may be wrong. Also when enabling devslp set the devslp-present bit in each enabled port. Also remove much of the 0:1f.2@0x98 setup and the attempt to write (the write once) CAP register that is already being written in the reference code. BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus Original-Change-Id: I467f3c15b9f4d4c814ba0ef8baf95739b4bc6662 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212308 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 9110a42982183b2954c865abbf18e008a39c997c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I7db5c7ccf619aa28856388dd40f59495ef6d7e77 Reviewed-on: http://review.coreboot.org/8958 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Misc updates from 2.1.0 ref codeDuncan Laurie
- ADSP IRQ should be exclusive - HDA should write reg 0x43 even if disabled - A few clock gating tweaks based on ref code changes - Move SATA clock gating to sata.c where SIR changes are done - Add support for enabling Deep SX in AC/DC modes - CLKREQ VR Idle for enabled PCIE ports BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus Original-Change-Id: Icece58e32b7a5d2b359debd5516a230cae3fd48c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211611 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit c0e22ba043ed96bdddca4989b2f29d0e989f6fef) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If5f5e1666aa9660e31305ee6369f2febf6757b99 Reviewed-on: http://review.coreboot.org/8952 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-02-15x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointerKevin Paul Herbert
On x86, change the type of the address parameter in read8()/read16/read32()/write8()/write16()/write32() to be a pointer, instead of unsigned long. Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7784 Tested-by: build bot (Jenkins)
2014-10-22broadwell: add new intel SOCDuncan Laurie
broadwell: Import files from haswell/lynxpoint into soc/broadwell Reviewed-on: https://chromium-review.googlesource.com/198425 (cherry picked from commit 178400e5709d676dd41e6a75df06faa829e0e3af) broadwell: Unify and clean up license Reviewed-on: https://chromium-review.googlesource.com/198426 (cherry picked from commit 30d3c25a0abc76be68477c39a654b95a5975f55d) broadwell: pch.h: split PM into new header Reviewed-on: https://chromium-review.googlesource.com/198427 (cherry picked from commit 97a8d0b051f476d0edc06301f57326a718df1373) broadwell: pch.h: split RCBA into new header Reviewed-on: https://chromium-review.googlesource.com/198428 (cherry picked from commit fa217361b28fdb8d3a3e85f070dfaf13c0d48135) broadwell: pch.h: split SATA into new header Reviewed-on: https://chromium-review.googlesource.com/198429 (cherry picked from commit bf8795ca92f9f0467e7869c701038abb4529ac71) broadwell: pch.h: split SPI into new header Reviewed-on: https://chromium-review.googlesource.com/198550 (cherry picked from commit 099af14676a2654ca3e24e66d7b9f0b4ab13cd14) broadwell: pch.h: split SerialIO into new header Reviewed-on: https://chromium-review.googlesource.com/198551 (cherry picked from commit 4f3c028686aed78fb07b8792dcf46aebd2268ea6) broadwell: pch.h: split LPC into new header Reviewed-on: https://chromium-review.googlesource.com/198552 (cherry picked from commit 10bad5bbb6739c0277fd5330d26a89d60fd5c102) broadwell: pch.h: split GPIO into new header and clean up Reviewed-on: https://chromium-review.googlesource.com/198553 (cherry picked from commit 9c97532460562215b78e10b011a29e092a07f3e5) broadwell: pch.h: split USB into new headers Reviewed-on: https://chromium-review.googlesource.com/198554 (cherry picked from commit 86ef1a45a2e5f307467b3be48e377569f37b3068) broadwell: Split IOBP into separate files Reviewed-on: https://chromium-review.googlesource.com/198734 (cherry picked from commit f93b8bda71728f1383937ad675d2d5fb5a927600) broadwell: smbus: Extract common code and split header Reviewed-on: https://chromium-review.googlesource.com/198735 (cherry picked from commit 8052030a9d6b22e8a19938fa9b93e90d08f0057d) broadwell: Create iomap.h header with platform base addresses Reviewed-on: https://chromium-review.googlesource.com/198736 (cherry picked from commit b35947d070b28871637dfe2b930a9f2be80958ee) broadwell: Add header for platform PCI devices Reviewed-on: https://chromium-review.googlesource.com/198737 (cherry picked from commit 6ac4e56db6e489bb9eaf91a0c3c543399f691500) broadwell: Split SMM related defines/prototypes to new header Reviewed-on: https://chromium-review.googlesource.com/198738 (cherry picked from commit 2a2595067077cd918bfd48cad79a684b8e1ff0f4) broadwell: cpu.h: Split MSR defines to separate header Reviewed-on: https://chromium-review.googlesource.com/198739 (cherry picked from commit 01148cd2c9edd97cd0c8ef3cfed58bc8c33eb805) broadwell: Create romstage header file Reviewed-on: https://chromium-review.googlesource.com/198740 (cherry picked from commit 31c91e811b9e07e7bcba6b9f8f5720a31322eb21) broadwell: Create ram stage header file Reviewed-on: https://chromium-review.googlesource.com/198741 (cherry picked from commit 93dde85f98d43d4a1886b59004d1bab4924ad621) broadwell: Add reference code data interface Reviewed-on: https://chromium-review.googlesource.com/198743 (cherry picked from commit 9059b8e2308892a48c838c3099404c9cf450df95) broadwell: Clean up ACPI NVS region Reviewed-on: https://chromium-review.googlesource.com/198897 (cherry picked from commit d83cc82c36661556eb1e2e437b7ac51d5b8e4a14) broadwell: Move CTDP ACPI methods to new file Reviewed-on: https://chromium-review.googlesource.com/198898 (cherry picked from commit fc1e711290df304d18c558d697eea8a5e57061b2) broadwell: Split EHCI and XHCI ACPI devices Reviewed-on: https://chromium-review.googlesource.com/198899 (cherry picked from commit 26f437b27e00dbd5c92ea22e76404633a62fb7ca) broadwell: ACPI: Clean up SerialIO ACPI code Reviewed-on: https://chromium-review.googlesource.com/198910 (cherry picked from commit ea3cd39566c1bb2ead463a6253b6204a62545d35) broadwell: ACPI: Remove special handling of LPT-LP chipset Reviewed-on: https://chromium-review.googlesource.com/198911 (cherry picked from commit 2c54df159bf6759c8f866628e83541de6f4e28f6) broadwell: ACPI: Clean up use of base address defines Reviewed-on: https://chromium-review.googlesource.com/198912 (cherry picked from commit 34e4788955bceff01631fd0b4dbf0aa24cf56b75) broadwell: ACPI: Clean up and fix formatting Reviewed-on: https://chromium-review.googlesource.com/198913 (cherry picked from commit bc0f7c6d2f95681eb987bb6ff6baf2d16cc77050) broadwell: Add header for ACPI defines and prototypes Reviewed-on: https://chromium-review.googlesource.com/198914 (cherry picked from commit 9951e7931942d2921f92f6e094b1cc32c190eab9) broadwell: Add reset_system function and header Reviewed-on: https://chromium-review.googlesource.com/198915 (cherry picked from commit 6d1efb94bd39bcd6f7e3e0de2f3299a384b109ef) broadwell: Move PCODE MMIO defines to systemagent.h Reviewed-on: https://chromium-review.googlesource.com/198916 (cherry picked from commit abb5f87e548fbde3a08e14a18714b4e4391c955f) broadwell: Unify chip.h and add chip.c Reviewed-on: https://chromium-review.googlesource.com/198917 (cherry picked from commit a9c2d7ff3afa1e2a10be85ccc72b7db0f2aaafe1) broadwell: Rename HASWELL_BCLK to CPU_BCLK Reviewed-on: https://chromium-review.googlesource.com/198918 (cherry picked from commit 65ac1a07abaf14eb42fec6c5df67d2d3688ad5a1) broadwell: Clean up broadwell/cpu.h Reviewed-on: https://chromium-review.googlesource.com/198919 (cherry picked from commit 17353803babc8ace279e105c012130678226144e) broadwell: Clean up broadwell/systemagent.h Reviewed-on: https://chromium-review.googlesource.com/198920 (cherry picked from commit 49d7a023f3ff04a65d16622aa9b2fa6004b693ae) broadwell: Clean up broadwell/pch.h Reviewed-on: https://chromium-review.googlesource.com/198921 (cherry picked from commit 17da652b4408a91fcfea99dd35fe9f9e1bdcf03b) broadwell: Clean up management engine driver Reviewed-on: https://chromium-review.googlesource.com/198922 (cherry picked from commit 4fce5fbb56dc4f31b77e5ada05463c043ad5be72) broadwell: Add common CPUID and PCI Device ID defines Reviewed-on: https://chromium-review.googlesource.com/198923 (cherry picked from commit c6bf20309f33168ea2cc4634cbda5ec242824ba8) broadwell: Clean up and expand report_platform Reviewed-on: https://chromium-review.googlesource.com/198924 (cherry picked from commit 5082d4824db149e867a2cd8be34c932b03754022) broadwell: Clean up the bootblock code Reviewed-on: https://chromium-review.googlesource.com/198925 (cherry picked from commit ba0206ab76fe0b6834a14dc57f400d139094623c) broadwell: Clean up ramstage device and driver operations Reviewed-on: https://chromium-review.googlesource.com/199180 (cherry picked from commit d8fc9daf129738713a5059286b7ead004f3b7569) broadwell: Clean up XHCI and EHCI ramstage drivers Reviewed-on: https://chromium-review.googlesource.com/199181 (cherry picked from commit d355247333a828a146ce7cf9b92a63da74119c1d) broadwell: Clean up gpio handling code Reviewed-on: https://chromium-review.googlesource.com/199182 (cherry picked from commit d62cef1970fe75f8166315016b3d8415cddcab20) broadwell: Clean up the PCH generic code Reviewed-on: https://chromium-review.googlesource.com/199183 (cherry picked from commit 3b93b3ea79965d5ac831bf9015e49330f157b0ff) broadwell: Move get_top_of_ram() and cbmem_top() to memmap.c Reviewed-on: https://chromium-review.googlesource.com/199184 (cherry picked from commit 68955ba4ff8b49ff466d7badaa934bd143026ba7) broadwell: Clean up pmutil.c Reviewed-on: https://chromium-review.googlesource.com/199185 (cherry picked from commit b6fb672ae879e17422f7449f70c3669055096f84) broadwell: pmutil: Add new acpi_sci_irq() function Reviewed-on: https://chromium-review.googlesource.com/199186 (cherry picked from commit 80ad8bb9bdc75f180e667861fed42a3844226bc5) broadwell: Clean up HDA ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199187 (cherry picked from commit b4962acd706eaa66c1c3ef4d22eba313642fbb2d) broadwell: Clean up cache_as_ram assembly Reviewed-on: https://chromium-review.googlesource.com/199188 (cherry picked from commit 8a457b82610b604ae7f69e2500815ce411c2d02d) broadwell: romstage: Separate stack helper functions Reviewed-on: https://chromium-review.googlesource.com/199189 (cherry picked from commit c220383c90466fc2dbf4b6107679b08ecb4aadad) broadwell: Add function to read WPSR from SPI Reviewed-on: https://chromium-review.googlesource.com/199190 (cherry picked from commit 935404da1157d606b913eff6c2635ae898e9980a) broadwell: Clean up SMBUS code in romstage and ramstage Reviewed-on: https://chromium-review.googlesource.com/199191 (cherry picked from commit 6ae9d93c1a6f14da6429a4e5b01619c9ccaefdaa) broadwell: SPI: Clean up romstage and ramstage code Reviewed-on: https://chromium-review.googlesource.com/199192 (cherry picked from commit 28ffd71a416aee2ab54bc5d782cfeef31d4d30bf) broadwell: Clean up PCIe root port ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199193 (cherry picked from commit 781f3a1b72c72f0bb05f5524edec471ad13ec90e) broadwell: Clean up minihd ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199194 (cherry picked from commit a52d275e41fdcbf9895d07350725609d9be1ff0e) broadwell: Update romstage main to follow baytrail format Reviewed-on: https://chromium-review.googlesource.com/199361 (cherry picked from commit 0678c739af84c871922ffba5594132b25e471ddd) broadwell: Add CPU set_max_freq function for romstage Reviewed-on: https://chromium-review.googlesource.com/199362 (cherry picked from commit 68b0122472af27f38502d42a8a6c80678ddbbba6) broadwell: romstage: Add chipset_power_state implementation Reviewed-on: https://chromium-review.googlesource.com/199363 (cherry picked from commit 761cec3b6bb9bde579c3214f3f1196f65700757c) broadwell: romstage: Convert systemagent init to reg_script Reviewed-on: https://chromium-review.googlesource.com/199364 (cherry picked from commit c2ea2d3a0c7555a353fb9a1d4a63e773ac8961b2) broadwell: romstage: Convert pch init to reg_script Reviewed-on: https://chromium-review.googlesource.com/199365 (cherry picked from commit 4383de5846e97ca5aee6dd210459d8dba0af981c) broadwell: elog: Use chipset_power_state for events Reviewed-on: https://chromium-review.googlesource.com/199366 (cherry picked from commit 0ef5961ebe3a7037d5fbe361fbc70a87ac2edad9) broadwell: Clean up SATA ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199367 (cherry picked from commit ffa5743f74551bd48aa7e5445ce7cd9dc7b07ce8) broadwell: Update ramstage graphics driver to support broadwell Reviewed-on: https://chromium-review.googlesource.com/199368 (cherry picked from commit bb01deb8bbed56f15e1143504e4cf012ecf5a281) broadwell: Update raminit to follow baytrail layout Reviewed-on: https://chromium-review.googlesource.com/199369 (cherry picked from commit 3f25c23dc58f85d2521916cd6edbe9deeeb8d523) broadwell: Update and unify the finalize steps Reviewed-on: https://chromium-review.googlesource.com/199390 (cherry picked from commit ddc4c116b42d38dfdfc45ef4388fbfab32ca48fa) broadwell: Clean up SMM code Reviewed-on: https://chromium-review.googlesource.com/199391 (cherry picked from commit 8295e56c9b643fd4b9267d70b5efd0cf94dd67dd) broadwell: Clean up LPC ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199392 (cherry picked from commit 28326aeaaf304c9262866588d91b79b37d1d9a2e) broadwell: Clean up systemagent ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199393 (cherry picked from commit 749988fff07eab8d2c9ebc731e3ed9e427b3f7b3) broadwell: Move C-state configuration information to acpi.c Reviewed-on: https://chromium-review.googlesource.com/199394 (cherry picked from commit 198a3cd5cbd009be406298cbb53163f075fe9990) broadwell: Clean up CPU ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199395 (cherry picked from commit 8159689bba479bab6fd2e949e3e1c3f817088969) broadwell: Do not reserve SMM relocation region Reviewed-on: https://chromium-review.googlesource.com/199402 (cherry picked from commit e2ab52340e3d3a97a3f8dbdad8fac9f7769d1b4c) broadwell: Add an early ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199403 (cherry picked from commit c7a8c867101b49a7f9f17ec1a8777a8db145f3e3) broadwell: Support for second reference code binary Reviewed-on: https://chromium-review.googlesource.com/199404 (cherry picked from commit abb99b36e97c4f739b23abed6146fea370bbbec2) broadwell: Clean up serialio init code Reviewed-on: https://chromium-review.googlesource.com/199405 (cherry picked from commit e09a1f8520a7b72451a1e2068b200f7c5451f489) broadwell: acpi: Add function to fill out FADT Reviewed-on: https://chromium-review.googlesource.com/199406 (cherry picked from commit 7e58f43e46d4382cf4541057f81fe6be3e4d6e74) broadwell: Update C-state table creation Reviewed-on: https://chromium-review.googlesource.com/199407 (cherry picked from commit 68b1f70e32e1d0c6fc4332dce402ad78334e0063) broadwell: acpi: Clean up acpi table creation code Reviewed-on: https://chromium-review.googlesource.com/199408 (cherry picked from commit 49088b312b159bb17a9330eda6a88d6f324ea146) broadwell: acpi: Add ACPI table create helper functions Reviewed-on: https://chromium-review.googlesource.com/199409 (cherry picked from commit 344c3c511d0341457525ef4d6eb70201404fc62c) broadwell: Add soc/intel/broadwell Makefiles Reviewed-on: https://chromium-review.googlesource.com/199410 (cherry picked from commit ea8f97738eadd3b0b6a642754df7a7d22e547ffc) broadwell: Add Kconfig for broadwell soc Reviewed-on: https://chromium-review.googlesource.com/199411 (cherry picked from commit 8c99038a5c20812497619134c66d45bc4f21c8fe) Squashed 78 commits for broadwell that form a solid code base. Change-Id: I365ca9a45978b5e0cc5237f884e20a44f62a0e63 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6964 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Marc Jones <marc.jones@se-eng.com>