coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-05-01	soc/intel/broadwell: Fix 16-bit read/write PCI_COMMAND register	Elyes HAOUAS
2020-04-06	soc/intel/broadwell: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2019-12-19	src/soc/intel: Remove unused <stdlib.h>	Elyes HAOUAS
2019-07-18	soc/intel: Use config_of()	Kyösti Mälkki
2019-03-16	src: Drop unused 'include <device/pciexp.h>'	Elyes HAOUAS
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
2019-03-04	device/mmio.h: Add include file for MMIO ops	Kyösti Mälkki
2019-03-01	device/pci: Fix PCI accessor headers	Kyösti Mälkki
2017-07-13	soc/intel: add IS_ENABLED() around Kconfig symbol references	Martin Roth
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-04-07	broadwell: Change all SoC headers to <soc/headername.h> system	Julius Werner
2015-02-15	x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer	Kevin Paul Herbert
2014-10-22	broadwell: ACPI, romstage, and other updates	Duncan Laurie
2014-10-22	broadwell: add new intel SOC	Duncan Laurie