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2017-03-10soc/intel/broadwell: Rework IGD's CDClk selectionNico Huber
CDClk selection was wrong in some corner cases (e.g. ULX SKUs) and, for Broadwell, never took the devicetree config into account. Rewrite the selection with the following in mind: o cpu_is_ult() might return `true` for ULX SKUs, too, o ULX and Broadwell-ULT SKUs can be `overclocked` with additional cooling, so leave that as devicetree option. For Haswell, the following frequency selections are valid: o ULX: 337.5MHz by default, 450MHz optional o ULT: 450MHz only (maybe 337.5MHz too, documentation varies, it wasn't selectable before either) o others: 540MHz by default, 450MHz optional For Broadwell: o ULX: 450MHz by default, 337.5MHz / 540MHz optional o ULT: 540MHz by default, 337.5MHz / 450MHz / 675MHz optional o others: 667MHz by default, 337.5MHz / 450MHz / 540MHz optional Side effects: A too high setting in the devicetree results in the highest possible frequency now, Haswell non-ULT/ULX defaults to 540MHz instead of 450MHz. Change-Id: Iec12752f2a47bf4a5ae6077c75790eae9378c1b2 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/17768 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-03-02intel/broadwell: Use the correct SATA port config for setting IOBP registerYouness Alaoui
Fix a typo that was introduce in commit 696ebc2d (Broadwell/Sata: Add support for setting IOBP registers for Ports 2 and 3.) [1]. Setting one of the SATA port 3 IOBP setting was using the value from the port 2 register. On the purism/librem13 (on which SATA port 3 is tested), this change doesn't seem to affect anything, as that typo wasn't exhibiting any visible problems anyways. [1] https://review.coreboot.org/18408 Change-Id: I3948def5c0588791009c4b24cbc061552d9d1d48 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/18514 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-02-22Broadwell/Sata: Add support for setting IOBP registers for Ports 2 and 3.Youness Alaoui
The Broadwell SATA controller supports IOBP registers on ports 0 and 1 but Browell supports up to 4 ports, so we need to support setting IOBP for ports 2 and 3 as well. The magic numbers (IOBP SECRT88 and DTLE) for ports 2 and 3 were only guessed by looking at ports 0 and 1 and extrapolating from there. Port 3 has been tested (DTLE setting on Librem 13) and confirmed to work so we can assume that port 2 and 3 magic numbers are valid, but having someone confirm them (through non-public documents?) would be great. Change-Id: I59911cfa677749ceea9a544a99b444722392e72d Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/18408 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-20lynxpoint/broadwell: fix PCH power optimizerMatt DeVillier
Setting both bits 27 and 7 of PCH register PMSYNC_CFG (PMSYNC Configuration; offset 0x33c8) causes pre-OS display init to fail on HSW-U/Lynxpoint and BDW-U ChromeOS devices when the VBIOS/GOP driver is run after the register is set. A re-examination of Intel's reference code reveals that bit 7 should be set for the LP PCH, and bit 27 for non-LP, but not both simultaneously. The previous workaround was to disable the entire power optimizer section via a Kconfig option, which isn't ideal. Test: unset bit 27 of PMSYNC_CFG and boot google/lulu, observe functional pre-OS video output Change-Id: I446e169d23dd446710a1648f0a9b9599568b80aa Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/18385 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-20Revert "intel/lynxpoint,broadwell: Fix eDP display in Windows, SeaBios & Tiano"Matt DeVillier
We've been able to narrow down the problem to a single register/ single bit, so revert this commit and address the problem in a follow-on commit. This reverts commit 0f2025da0fd4dce6b951b4c4b97c9370ca7d66db. Change-Id: I780f9ea2976dd223aaa3e060aef6e1af8012c346 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/18384 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-27cpu/intel/common: Add/Use common function to set virtualizationMatt DeVillier
Migrate duplicated enable_vmx() method from multiple CPUs to common folder. Add common virtualization option for CPUs which support it. Note that this changes the default to enable virtualization on CPUs that support it. Change-Id: Ib110bed6c9f5508e3f867dcdc6f341fc50e501d1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17874 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2016-12-23spi: Get rid of SPI_ATOMIC_SEQUENCINGFurquan Shaikh
SPI_ATOMIC_SEQUENCING was added to accomodate spi flash controllers with the ability to perform tx and rx of flash command and response at the same time. Instead of introducing this notion at SPI flash driver layer, clean up the interface to SPI used by flash. Flash uses a command-response kind of communication. Thus, even though SPI is duplex, flash command needs to be sent out on SPI bus and then flash response should be received on the bus. Some specialized x86 flash controllers are capable of handling command and response in a single transaction. In order to support all the varied cases: 1. Add spi_xfer_vector that takes as input a vector of SPI operations and calls back into SPI controller driver to process these operations. 2. In order to accomodate flash command-response model, use two vectors while calling into spi_xfer_vector -- one with dout set to non-NULL(command) and other with din set to non-NULL(response). 3. For specialized SPI flash controllers combine two successive vectors if the transactions look like a command-response pair. 4. Provide helper functions for common cases like supporting only 2 vectors at a time, supporting n vectors at a time, default vector operation to cycle through all SPI op vectors one by one. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: I4c9e78c585ad95c40c0d5af078ff8251da286236 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17681 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-15soc/intel/common: remove mrc cache assumptionsAaron Durbin
Update the mrc cache implementation to use region_file. Instead of relying on memory-mapped access and pointer arithmetic use the region_devices and region_file to obtain the latest data associated with the region. This removes the need for the nvm wrapper as the region_devices can be used directly. Thus, the library is more generic and can be extended to work on different boot mediums. BUG=chrome-os-partner:56151 Change-Id: Ic14e2d2f7339e50256b4a3a297fc33991861ca44 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17717 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-14soc/intel/broadwell/lpc.c: don't zeroize existing gnvs tableMatt DeVillier
The gnvs table only needs to be zeroized after init; zeroizing an existing/populated table renders all I2C devices completely non-functional. TEST: boot Linux and observe all I2C devices functional Change-Id: Id149ad645dfe5ed999a65d10e786e17585abc477 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17828 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-07soc/broadwell: set EM4/EM5 registers based on cdclkMatt DeVillier
The EM4/EM5 registers in the mini-HD audio device must be set based on the GPU cdclk value in order for HDMI audio to function properly. Add variables to save the correct values when initializing the GPU, and accessor functions to retrieve them in order to set the registers when initializing the mini-HD audio device. Change-Id: Icce7d5981f0b2ccb09d3861b28b843a260c8aeba Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17718 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-07MMCONF_SUPPORT: Flip default to enabledKyösti Mälkki
Also remove separate MMCONF_SUPPORT_DEFAULT flag. Change-Id: Idf1accdb93843a8fe2ee9c09fb984968652476e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17694 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07PCI ops: MMCONF_SUPPORT_DEFAULT is requiredKyösti Mälkki
Doing PCI config operations via MMIO window by default is a requirement, if supported by the platform. This means chipset or CPU code must enable MMCONF operations early in bootblock already, or before platform-specific romstage entry. Platforms are allowed to have NO_MMCONF_SUPPORT only in the case it is actually not implemented in the silicon. Change-Id: Id4d9029dec2fe195f09373320de800fcdf88c15d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17693 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06PCI ops: Define read-modify-write routines globallyKyösti Mälkki
Change-Id: I7d64f46bb4ec3229879a60159efc8a8408512acd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17690 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06intel PCI ops: Remove explicit PCI MMCONF accessKyösti Mälkki
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access being non-atomic and/or need to access 4kiB of PCI config space. All these platforms now have MMCONF_SUPPORT_DEFAULT. Change-Id: If62537475eb67b7ecf85f2292a2a954a41bc18d1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17545 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-05spi: Define and use spi_ctrlr structureFurquan Shaikh
1. Define a new structure spi_ctrlr that allows platforms to define callbacks for spi operations (claim bus, release bus, transfer). 2. Add a new member (pointer to spi_ctrlr structure) in spi_slave structure which will be initialized by call to spi_setup_slave. 3. Define spi_claim_bus, spi_release_bus and spi_xfer in spi-generic.c which will make appropriate calls to ctrlr functions. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Icb2326e3aab1e8f4bef53f553f82b3836358c55e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17684 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-05spi: Pass pointer to spi_slave structure in spi_setup_slaveFurquan Shaikh
For spi_setup_slave, instead of making the platform driver return a pointer to spi_slave structure, pass in a structure pointer that can be filled in by the driver as required. This removes the need for platform drivers to maintain a slave structure in data/CAR section. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Ia15a4f88ef4dcfdf616bb1c22261e7cb642a7573 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17683 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-05spi: Fix parameter types for spi functionsFurquan Shaikh
1. Use size_t instead of unsigned int for bytes_out and bytes_in. 2. Use const attribute for spi_slave structure passed into xfer, claim bus and release bus functions. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Ie70b3520b51c42d750f907892545510c6058f85a Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17682 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-04spi_flash: Move spi flash opcodes to spi_flash.hFurquan Shaikh
BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: I3b6656923bb312de470da43a23f66f350e1cebc7 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17680 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-01romstage_handoff: remove code duplicationAaron Durbin
The same pattern was being used throughout the code base for initializing the romstage handoff structure. Provide a helper function to initialize the structure with the S3 resume state then utilize it at all the existing call sites. Change-Id: I1e9d588ab6b9ace67757387dbb5963ae31ceb252 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17646 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-11-22Remove explicit select MMCONF_SUPPORTKyösti Mälkki
Make MMCONF_SUPPORT selected with MMCONF_SUPPORT_DEFAULT. Platforms that remain to have explicit MMCONF_SUPPORT are ones that should be converted. Change-Id: Iba8824f46842607fb1508aa7d057f8cbf1cd6397 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17527 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-18intel post-car: Increase stacktop alignmentKyösti Mälkki
Align top of stack to 8 bytes, value documented as FSP1.1 requirement. Also fix some cases of uintptr_t casted to unsigned long. Change-Id: I5bbd100eeb673417da205a2c2c3410fef1af61f0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17461 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-08intel car: Remove references to DCACHE_RAM_ROMSTACK_SIZEKyösti Mälkki
Not referenced in code. Change-Id: Iea91f4418eb122fb647ec0f4f42cb786e8eadf23 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17268 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-31lib/prog_loaders: use common ramstage_cache_invalid()Aaron Durbin
All current implementations of ramstage_cache_invalid() were just resetting the system based on the RESET_ON_INVALID_RAMSTAGE_CACHE Kconfig option. Move that behavior to a single implementation within prog_loaders.c which removes duplication. Change-Id: I67aae73f9e1305732f90d947fe57c5aaf66ada9e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17184 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-19intel/broadwell: "free" memory after usePatrick Georgi
While we stub out free(), tools like coverity scan have no idea, and it might change in the future. So free it. Change-Id: I1d93a6f45b64445662daa95b51128140ad0a87e2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1260716 Reviewed-on: https://review.coreboot.org/17055 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-10-02Kconfig: Update default hex values to start with 0xMartin Roth
Kconfig hex values don't need to be in quotes, and should start with '0x'. If the default value isn't set this way, Kconfig will add the 0x to the start, and the entry can be added unnecessarily to the defconfig since it's "different" than what was set by the default. A check for this has been added to the Kconfig lint tool. Change-Id: I86f37340682771700011b6285e4b4af41b7e9968 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16834 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-08-31src/soc: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: Ifc47f103492a2cd6c818dfd64be971d34afbe0a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16324 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-19Kconfig: introduce writable boot device notionAaron Durbin
Indicate to the build system that a platform provides support for a writable boot device. The following will provide the necessary support: COMMON_CBFS_SPI_WRAPPER users soc/intel/apollolake soc/intel/baytrail soc/intel/braswell soc/intel/broadwell soc/intel/skylake The SPI_FLASH option is auto-selected if the platform provides write supoprt for the boot device and SPI flash is the boot device. Other platforms may provide similar support, but they do that in a device specific manner such as selecting SPI_FLASH explicitly. This provides clearance against build failures where chipsets don't provide SPI API implementations even though the platform may use a SPI flash to boot. BUG=chrome-os-partner:56151 Change-Id: If78160f231c8312a313f9b9753607d044345d274 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16211 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-08chromeos chipsets: select RTC usageAaron Durbin
Since RTC is now a Kconfig ensure RTC is selected on the x86 chipsets which are in Chrome OS devices. This allows the eventlog to have proper timestamps instead of all zeros. BUG=chrome-os-partner:55993 Change-Id: I24ae7d9b3bf43a5791d4dc04aae018ce17fda72b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16086 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-02intel/lynxpoint,broadwell: Fix eDP display in Windows, SeaBios & TianoPrabal Saha
Without this patch, eDP output is non-functional pre-graphics driver regardless of payload (SeaBIOS, Tianocore) or video init method (VBIOS, GOP driver) and once the standard Windows Intel HD graphics driver is loaded. Test: Boot Windows on peppy and auron_paine, install Intel HD Graphics driver, observe functional eDP output with full video acceleration. Debugging method: adjust location of call to run VBIOS within coreboot, observed that eDP output functional if the VBIOS is run before the power optimizer lines, broken if run afterwards. Change-Id: I6d8252e3de396887c84533e355f41693b9ea7514 Signed-off-by: Prabal Saha <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/15261 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-31src/soc: Capitalize CPU, ACPI, RAM and ROMElyes HAOUAS
Change-Id: I7f0d3400126d593bad8e78f95e6b9a378463b4ce Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15963 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-31intel/broadwell: fix typoPatrick Georgi
(pci_read_config32(...) > 14) & 0x3 looks rather unusual (and prevents "case 3" below from ever happening) Change-Id: Id90655c39ff53da9569441278bbf73497d643480 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1293139 Reviewed-on: https://review.coreboot.org/15965 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-30chromeos mainboards: remove chromeos.aslAaron Durbin
Use the ACPI generator for creating the Chrome OS gpio package. Each mainboard has its own list of Chrome OS gpios that are fed into a helper to generate the ACPI external OIPG package. Additionally, the common chromeos.asl is now conditionally included based on CONFIG_CHROMEOS. Change-Id: I1d3d951964374a9d43521879d4c265fa513920d2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15909 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28soc/intel/broadwell: Use init_vbnv_cmos from vboot vbnvFurquan Shaikh
BUG=chrome-os-partner:55639 Change-Id: Ie38cdbec513e2bb66e276399c8b4490cbe34a747 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15924 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2016-07-28bootmode: Get rid of CONFIG_BOOTMODE_STRAPSFurquan Shaikh
With VBOOT_VERIFY_FIRMWARE separated from CHROMEOS, move recovery and developer mode check functions to vboot. Thus, get rid of the BOOTMODE_STRAPS option which controlled these functions under src/lib. BUG=chrome-os-partner:55639 Change-Id: Ia2571026ce8976856add01095cc6be415d2be22e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15868 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-28vboot: Separate vboot from chromeosFurquan Shaikh
VBOOT_VERIFY_FIRMWARE should be independent of CHROMEOS. This allows use of verified boot library without having to stick to CHROMEOS. BUG=chrome-os-partner:55639 Change-Id: Ia2c328712caedd230ab295b8a613e3c1ed1532d9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15867 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-15soc/intel/broadwell: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: I99d909ee72c3abebb1e9c8ebf44137465264bf0d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15673 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-10intel post-car: Consolidate choose_top_of_stack()Kyösti Mälkki
Change-Id: I2c49d68ea9a8f52737b6064bc4fa703bdb1af1df Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15463 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-29intel romstage: Use run_ramstage()Kyösti Mälkki
Change-Id: I22a33e6027a4e807f7157a0dfafbd6377bc1285d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15461 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22Ignore RAMTOP for MTRRsKyösti Mälkki
Without RELOCATABLE_RAMSTAGE have WB cache large enough to cover the greatest ramstage needs, as there is no benefit of trying to accurately match the actual need. Choose this to be bottom 16MiB. With RELOCATABLE_RAMSTAGE write-back cache of low ram is only useful for bottom 1MiB of RAM as a small part of this gets used during SMP initialisation before proper MTRR setup. Change-Id: Icd5f8461f81ed0e671130f1142641a48d1304f30 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15249 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-19intel/broadwell: Remove old USBDEBUG backup store in CARKyösti Mälkki
Required EHCI state is maintained as a CAR_GLOBAL to have it properly migrated. Change-Id: I8df413bec6faae4952670710c8ac804e0331c966 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15236 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-06-18intel cache_as_ram: Fix typo in commentKyösti Mälkki
Change-Id: I2539e490e160e01cab2ad8d2086d2f242a88c640 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15223 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-17Fix some cbmem.h includesKyösti Mälkki
Change-Id: I36056af9f2313eff835be805c8479e81d0b742bf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15196 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-06{cpu,soc}/intel: remove unused smm_init() functionAaron Durbin
There used to be a need for an empty smm_init() function because initialize_cpus() called it even though nothing called initialize_cpus(). However, garbage collection at link time is implemented so there's no reason to provide an empty function to satisfy a symbol that is completely culled during link. Remove it. Change-Id: Ic13c85f1d3d57e38e7132e4289a98a95829f765a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14605 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-06soc/intel/broadwell: convert to using common MP and SMM initAaron Durbin
In order to reduce duplication of code use the common MP and SMM initialization flow. Change-Id: I74c81c5d18dff7a84bfedbe07f01e536c0f641fa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14595 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-05-04cpu/x86: remove BACKUP_DEFAULT_SMM_REGION optionAaron Durbin
Unconditionally provide the backup default SMM area API. There's no reason to guard the symbols behind anything since linker garbage collection is implemented. A board or chipset is free to use the code or not without needing to select an option. Change-Id: I14cf1318136a17f48ba5ae119507918190e25387 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14561 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-04broadwell/me: Fix out-of-bounds array access errorEvan Lojewski
Fix an issue where a broadwell machine without the ME installed could result in an invalid status code being reported. For certain values, this would result in the intel_me_status function never returning. Fix has been tested on a samus board w and w/o the ME blob installed. Change-Id: I96667d3b89393f161e4d4efe0544efac98367e6c Signed-off-by: Evan Lojewski <meklort@gmail.com> Reviewed-on: https://review.coreboot.org/14409 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-05-02cpu/x86/mp_init: remove unused callback argumentsAaron Durbin
The BSP and AP callback declarations both had an optional argument that could be passed. In practice that functionality was never used so drop it. Change-Id: I47fa814a593b6c2ee164c88d255178d3fb71e8ce Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14556 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-04-14soc/intel: Update license headersMartin Roth
Update all of the license headers to make sure they are compliant with coreboot's license header policy. Change-Id: I151d058615290e528d9d1738c17804f6b9cc8dce Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14321 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-08x86 chipsets: utilize x86_setup_mtrrs_with_detect()Aaron Durbin
For all the chipsets which were performing the following sequence: x86_setup_fixed_mtrrs(); x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2); Replace that with x86_setup_mtrrs_with_detect() since it is equivalent. Change-Id: I9f362dbf38942d675f615d22b9e5770ce65e5a08 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13936 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-02-09chromeos: Remove CONFIG_VBNV_SIZE variableDuncan Laurie
The VBNV region size is determined by vboot and is not really configurable. Only the CMOS implementation defined this config variable so switch it to use VBNV_BLOCK_SIZE defined by vboot in vbnv_layout.h instead. This requires updating the broadwell/skylake cmos reset functions to use the right constant. BUG=chrome-os-partner:47915 BRANCH=glados TEST=manually tested on chell Change-Id: I45e3efc2a22efcb1470bbbefbdae4eda33fc6c96 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e2b803ff3ac30ab22d65d1e62aca623730999a1d Original-Change-Id: I4896a1a5b7889d77ad00c4c8f285d184c4218e17 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/324520 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13598 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-27 04:48:50 +0000