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path: root/src/soc/intel/broadwell
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2015-05-27Move TPM code out of chromeosVladimir Serbinenko
This code is not specific to ChromeOS and is useful outside of it. Like with small modifications it can be used to disable TPM altogether. Change-Id: I8c6baf0a1f7c67141f30101a132ea039b0d09819 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10269 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-26acpigen: Remove all explicit length trackingVladimir Serbinenko
Change-Id: I88248d78c01b4b4e42a097889b5f4ddfdac3d966 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7367 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2015-05-26acpi: Remove monolithic ACPIVladimir Serbinenko
All boards now use per-device ACPI. This patch finishes migration by removing transitional kludges. Change-Id: Ie4577f89bf3bb17b310b7b0a84b2c54e404b1606 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7372 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-20acpi: make fill_slit and fill_srat into arguments.Vladimir Serbinenko
SLIT and SRAT are created this way only on amdk8 and amdfam10. This saves the need of having a lot of dummies. Change-Id: I76d042702209cd6d11ee78ac22cf9fe9d30d0ca5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7052 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13baytrail: broadwell: correct refcode loadingAaron Durbin
I messed up the conditionals on loading the reference code. The bug used || instead of && causing 2 reference codes to be loaded. Change-Id: I29a046bf0e8dc29a9efdb636ebfd04e11eb73f82 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10185 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-05-053rdparty: move to 3rdparty/blobsPatrick Georgi
There's now room for other repositories under 3rdparty. Change-Id: I51b02d8bf46b5b9f3f8a59341090346dca7fa355 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10109 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-053rdparty: Move to blobsPatrick Georgi
To move 3rdparty to 3rdparty/blobs (ie. below itself from git's broken perspective), we need to work around it - since some git implementations don't like the direct approach. Change-Id: I1fc84bbb37e7c8c91ab14703d609a739b5ca073c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10108 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-01intel: Correct MMIO related ACPI table settingsDave Frodin
Several of the intel platforms define the region reserved for PCI memory resources in a location where it overlaps with the MMIO (MCFG) region. Using the memory map from mohon_peak as an example: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000a0000-00000000000fffff: RESERVED 3. 0000000000100000-000000007fbcffff: RAM 4. 000000007fbd0000-000000007fbfffff: CONFIGURATION TABLES 5. 000000007fc00000-000000007fdfffff: RESERVED 6. 00000000e0000000-00000000efffffff: RESERVED 7. 00000000fee00000-00000000fee00fff: RESERVED 8. 0000000100000000-000000017fffffff: RAM The ACPI table describing the space set aside for PCI memory (not to be confused with the MMIO config space) is defined as the region from BMBOUND (the top of DRAM below 4GB) to a hardcoded value of 0xfebfffff. That region would overlap the MMIO region at 0xe0000000-0xefffffff. For rangeley the upper bound of the PCI memory space should be set to 0xe0000000 - 1. The MCFG regions for several of the affected chipsets are: rangeley 0xe0000000-0xefffffff baytrail 0xe0000000-0xefffffff haswell 0xf0000000-0xf3ffffff sandybridge 0xf8000000-0xfbffffff TEST = intel/mohonpeak and intel/bayleybay. Change-Id: Ic188a4f575494f04930dea4d0aaaeaad95df9f90 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/9972 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2015-04-30intel/broadwell: Allow using non-fake IFD descriptorPatrick Georgi
Change-Id: I3091437444ffd9ca3e103c41c37a5374805b1231 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10045 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-04-30intel/broadwell: bootstate mechanism only exists in ramstagePatrick Georgi
So don't try to use it elsewhere. Change-Id: Ia600ba654bde36d3ea8a0f3185afae00fe50bfe9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10030 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-30intel/broadwell: Don't select MONOTONIC_TIMER_MSRPatrick Georgi
That's a Haswell exclusive, used nowhere else, but confusing when hunting for the monotonic timer used on that SoC. Change-Id: I60ec523e54e5af0d2a418bcb9145de452a3a4ea9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10034 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-30intel/broadwell: Build monotonic timer driver for SMMPatrick Georgi
SPI flash drivers need it. Change-Id: I63d79472d70d75f7907e7620755c228d5a4918e1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10033 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-30chromeos: Add missing headersPatrick Georgi
Builds with CHROMEOS fail due to missing includes. Change-Id: I8c88bca8f8cc3247d3f3311777f794c4fdfee3c1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10029 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-30kbuild: Don't require intel/common changes for every socStefan Reinauer
In the true spirit of separating components more strictly and allowing to add new components to coreboot without touching existing code, move Intel common code selection to the soc Kconfig and out of src/soc/intel/common/Makefile.inc Change-Id: I0a70656bb9f4550b6088e9f45e68b5106c0eb9af Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10031 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-29kbuild: automatically include SOCsStefan Reinauer
This change switches all SOC vendors and southbridges to be autoincluded by Makefile.inc, rather than having to be mentioned explicitly in soc/Makefile.inc or in soc/<vendor>/Makefile.inc. This means, vendor and SOC directories are now "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree components to be built with a given coreboot version (given that the API did not change). Change-Id: Iede26fe184b09c53cec23a545d04953701cbc41d Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9799 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-22intel/broadwell: guard CHROMEOS support betterPatrick Georgi
Since CHROMEOS_VBNV_* are selected by mainboards, they may be active without CHROMEOS being selected. In this case, they should be a no-op. Change-Id: I3b84e2a919ffaa809d713e72e5e4df7a7575e6b9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9954 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22coreboot: common stage cacheAaron Durbin
Many chipsets were using a stage cache for reference code or when using a relocatable ramstage. Provide a common API for the chipsets to use while reducing code duplication. Change-Id: Ia36efa169fe6bd8a3dbe07bf57a9729c7edbdd46 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8625 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-21broadwell: Clear USB3.0 PORTSC status bits in sleep_prepare.Todd Broch
Found that any non-USB3.0 devices connected to type-C ports (displayPort dongles) cause XHCI port to see connection which in turn leads us to enter USB compliance mode. That in turn causes the port to wake the system for a yet-to-be determined reason. Clearing the PORTSC status bits (actually just CSC) seems to remedy the wake. Signed-off-by: Todd Broch <tbroch@chromium.org> BRANCH=samus BUG=chrome-os-partner:35320 TEST=manual, 1. Plug hoho into type-C port on samus and remove 2. powerd_dbus_suspend Device stays asleep. Change-Id: Id3a291579ffca0152a7ef32e37ecae80ca08a82b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0be5cba4916681dceb0372e76d9643e6c7175db5 Original-Change-Id: I1396b9f8013dbbb31286c1d8958af592b3da7475 Original-Reviewed-on: https://chromium-review.googlesource.com/247410 Original-Commit-Queue: Todd Broch <tbroch@chromium.org> Original-Tested-by: Todd Broch <tbroch@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9814 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21broadwell: indent xhci codePatrick Georgi
Change-Id: I97920e7eb64c05034184f9a4e1c8f2dfa44d3fdd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9813 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21broadwell: Skip pre-graphics delay in resume pathDuncan Laurie
If the board is configured with a pre-graphics delay it should be skipped in the resume path. BUG=chrome-os-partner:28234 BRANCH=broadwell TEST=measure resume time in dev mode to be same as normal mode Change-Id: I5a4ad5bba9e5316c89f7935d8811759b041429d9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b44a7167532410fc44ca9df1c91c91aaf541ae49 Original-Change-Id: Ic9f2cda71d8a567f57e863409f0f3fb98ab68bcf Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/245116 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9812 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21broadwell: Implement Recovery ButtonRyan Lin
This patch fixes the use of the recovery button, and the value is stored in a SATA controller scratch register. BUG=chrome-os-partner:35241 BRANCH=none TEST=Use recovery button and run firmware_RecoveryButton Change-Id: Ia06f147c7e44d6c4eea2c2e4f502c233c956ee9b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 34c7ee922a9602b3448a72cd669fd68feeed1bba Original-Change-Id: I1667c7f188b0f87c4bc7caa82f9c977b2b4c0611 Original-Signed-off-by: Ryan Lin <ryan.lin@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241772 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9811 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-18broadwell: Set C9/C10 vccminDuncan Laurie
This is done via a PCODE mailbox write. BUG=chrome-os-partner:37043 BRANCH=broadwell TEST=build and boot on samus Change-Id: I95e8fe3e28eec76d6b5b488a0c770c04f408700e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b90bef7f708b1ce83f6e124f4b38ae51ec6b0597 Original-Change-Id: I95cd4c17db672a53ba05f85ba5fa7bc866af1543 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/252862 Original-Reviewed-by: Alec Berg <alecaberg@chromium.org> Original-Reviewed-by: Shawn N <shawnn@chromium.org> (cherry picked from commit ab6b4bddf3365713aa40d194c2dbd3e59985f00d) Original-Reviewed-on: https://chromium-review.googlesource.com/252883 Reviewed-on: http://review.coreboot.org/9783 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-18broadwell: Disable XHCI compliance mode entryDuncan Laurie
To avoid entries with Type-C alternate mode devices disable compliance mode entry. This needs to be set on both boot and resume. BUG=chrome-os-partner:35320 BRANCH=samus TEST=manual: 1) boot on samus with USB keyboard plugged in -> controller in D0 at boot 2) iotools mmio_read32 0xe12080ec == 0x18010c01 3) suspend and resume 4) iotools mmio_read32 0xe12080ec == 0x18010c01 5) remove USB keyboard -> controller in D3 6) iotools mmio_read32 0xe12080ec == 0xffffffff 7) plug in USB keyboard -> controller in D0 8) iotools mmio_read32 0xe12080ec == 0x18010c01 9) boot with no external USB devices -> controller in D3 at boot 10) iotools mmio_read32 0xe12080ec == 0xffffffff 11) plug in USB keyboard -> controller in D0 12) iotools mmio_read32 0xe12080ec == 0x18010c01 Change-Id: I4d566112b3c188bafdf9a4bbd92944c89500e3e8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: db8c8ab8ff25f6a39cd50dcc91b5ba9fd7d05059 Original-Change-Id: I8b68ba75e254a7e236c869f4470207eb5290053d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/251361 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9782 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-18broadwell: add ROM stage pre console init call backWenkai Du
Serial port on ITE 8772 SuperIO must be initialized before console_init is called. So the pre console init callback is added to let mainboard code do proper initialization. Change-Id: Iaa3e4b9c6e7ce77a7b9a6b9ecedd8ea54f3141dc Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 71ee2fd470e19fa4854f895678445b05c17761c1 Original-Change-Id: I594e6e4a72f65744deca5cad666eb3b227adeb24 Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/227933 Original-Reviewed-by: Kenji Chen <kenji.chen@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com> Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9472 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-15broadwell: Fixes for _SWS supportDuncan Laurie
- These should be 64bit values so when they try to return -1 it is interpreted properly by the kernel. - The GPE value needs to be reset at the start so it does not return stale data from a previous resume. - If a GPE register is zero the value should only be updated if it has not yet found a set bit. BUG=chrome-os-partner:34532 BRANCH=samus,auron TEST=build and boot on samus, suspend/resume with various wake sources and ensure the reported _SWS values are correct in every case. Original-Change-Id: Ic6897f20ad2f321f3566694c032b75a3db120556 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/235012 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit be3c79b87b81563f744eb885708a52730debaccb) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I801c6e4f90dde0f5f69685f987a9831ee5e99e4a Reviewed-on: http://review.coreboot.org/9699 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-15broadwell: Remove unused bootblock codeDuncan Laurie
This code that stores the initial timestamp is not being used, instead the timestamp is passed to romstage_main(). BUG=chrome-os-partner:28234 BRANCH=samus,auron TEST=build and boot on samus Original-Change-Id: I0e0fa1ba74ab93d4454fdfa12208e712d2ae913c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/234402 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> (cherry picked from commit 838112cf79e2b4d51e5dc87d5ac9cd7e03807f29) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8fd7ba72c14c1e39f7bfa3a1ae8d03289a2abf73 Reviewed-on: http://review.coreboot.org/9698 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-15broadwell: Clean up ME device and add new ME10 flowDuncan Laurie
In order to avoid a 300ms timeout waiting for mbp_cleared flag to be set there is a new flow for the ME10 1.5MB firwmare that we can follow which will save significant boot time. This requires sending new commands that do not generate an ACK message, and ensuring an HMRFPO LOCK message is sent. In addition now that the delay is removed clean up the ME path to do the work in init() step and add a final() step that does the disabling of the PCI device. BUG=chrome-os-partner:30637,chrome-os-partner:34134 BRANCH=samus,auron TEST=build and boot on samus, measure ~300ms speedup in boot time Original-Change-Id: I753087ecd65f6ebed9f812318a359f893e01da9f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/234400 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 25aff4b188dc94a99af30869a162e01e3fa8dee7) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia35373548a902a718155a1a57057f55067d2f3ac Reviewed-on: http://review.coreboot.org/9697 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-15soc/broadwell: Use microcode from the blobs repositoryMarc Jones
Remove the blobs from the coreboot tree and get them from 3rdparty. Change-Id: I4938b5c47e6ae7059eda144b664aeafdd674f0fb Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/9693 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-04-14broadwell: Remove TPM device from lpc.aslDuncan Laurie
This is not a standard feature so it should be included by the mainboard if it is actually present in a system. BUG=chrome-os-partner:33385 BRANCH=samus,auron TEST=build and boot on samus CQ-DEPEND=CL:226663, CL:226664 Change-Id: Id4d0e5ed243dcb95e64fb8c848667f651b75aa4e Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 8909913f5c11c5805c77a3373859634b02a301e2 Original-Change-Id: Ib7c171a5a007a2dddfb3d80341c6dc488e383e99 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226662 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9470 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13broadwell: Work around VBIOS framebuffer issueDuncan Laurie
The first 64 bytes of the framebuffer contain garbage after running the option rom and after calling the VBE mode set with the flag to clear the framebuffer. Work around this issue by clearing the first 64 bytes in the framebuffer in the broadwell graphics setup code after it executes the VBIOS. BUG=chrome-os-partner:32771 BRANCH=samus,auron TEST=build and boot on samus in dev mode, check for graphical corruption Change-Id: I0381e32a5ea17e13c4ed598835999c12136418cf Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: f29c1b0b7c100cf290f82de671042823032f71c9 Original-Change-Id: I072bc913f7daea16e4861a7549e1b4ec85cde4cd Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/222676 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9464 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-13broadwell: Fix incorrect SATA port map maskWenkai Du
WPT-LP has 4 SATA ports. Current code assumes 6 SATA ports and as a result, some reserved bits are written with 1. No specific issue has been observed so far. BUG=None BRANCH=None TEST=Verify SATA PCI configure space dump on Auron Change-Id: I737719b3d5cd788158cd5b6991405ba098be4078 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 2b55587a74ac5d45354dc123937b562290468855 Original-Change-Id: I9c53ac86e2bf72901647bd2cfa48ac0ce31abea0 Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/233661 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9479 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13broadwell: Enable double self refresh by defaultDuncan Laurie
Rather than enable this in every mainboard just enable it by default for all broadwell devices and let a specific mainboard disable it if needed. BUG=chrome-os-partner:34420 BRANCH=samus,auron TEST=build and boot on samus Change-Id: I6e47c20abf29abfbd1f4b7905914b4c9fadb0ae7 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 25d3a685893e1c85f7b78e302da3187947a1f84f Original-Change-Id: I26d9f2e2a12d3f2f888ecb5af0d949eec5928f57 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/238400 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9590 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Correct XHCI offset for USB 3.0 portsJulius Werner
Looks like Intel has added two more USB 2.0 ports from LynxPoint to Broadwell, which shifted the port offsets of the USB 3.0 ports behind them. The USB 2.0 ports are now 0x480 to 0x520 and the 3.0 ones 0x530 to 0x560 (at least according to what my kernel seems to think). The offset of the first USB 3.0 port is hardcoded and seems to have been copied over without accounting for this, meaning when we try to operate on all USB 3.0 ports we actually operate on the last two 2.0 and the first two 3.0 ports instead. This patch should fix the bug for now. In the future, we might want to consider dynamically detecting port locations through the Protocol Capability structures at the end of the XHCI register set instead. BRANCH=samus BUG=chrome-os-partner:35320 TEST=TODO Change-Id: Ifab6e484980fd4cd0daf80ceb292ddced2ab1aea Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 525f359c0b6b95b260add2b4617fd86119d69397 Original-Change-Id: Ic2becf2b043612270909ceef66e7d58efc8fcbe1 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/247351 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Todd Broch <tbroch@chromium.org> Reviewed-on: http://review.coreboot.org/9502 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Set PCIe replay timeout to 0xDDuncan Laurie
This changes the PCIe replay timeout value in the root ports to be 0xD to fix correctable AER replay timer timeout errors. BUG=chrome-os-partner:31551 BRANCH=broadwell TEST=build and boot on samus Change-Id: I3084cc633da6e9f9a783d923a3fe2c1097e711fd Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: a64897efc26731fa3896e6d9a413941807296a28 Original-Change-Id: I53d87ad38856fd7de7f3f06a805c9342373bc968 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/245359 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9501 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Add configuration for tuning VR for C-state operationsDuncan Laurie
Add some configuration options that allow tuning the VR for C-state settings that may be able to reduce noise. - Add option to enable slow VR ramp rate for C-state exit - Add variable to configure the minimum C6/C7 voltage BUG=chrome-os-partner:34771 BRANCH=broadwell TEST=build and boot on samus Change-Id: I01445d62fbfcf200b787b924d8d72685819a4715 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: ed8f355e60292c82791817ae31bff58ac2390a72 Original-Change-Id: I8af75b69c8b55d3e210170ee96f8e22c2fd76374 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241950 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9497 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Preserve VbNv around cmos_initDuncan Laurie
To ensure that boot flags (legacy, usb, signed-only) are properly restored from CMOS and used in the first boot after a battery removal or RTC reset then the VbNv region needs to be preserved around the cmos_init call. When using vboot firmware selection and VbNv is stored in CMOS then that region of CMOS will have been re-initialized by the time we call cmos_init and reset CMOS if the chipset flag was set indicating a problem. BUG=chrome-os-partner:35240 BRANCH=broadwell TEST=manual testing on samus: 1) boot in dev mode, enable dev_boot_legacy and ensure it works 2) on EC console pulse PCH_RTCRST_L low for a second 3) ensure first boot after RTC reset will still boot legacy mode 4) remove battery for a time 5) ensure first boot after battery is re-inserted will still boot legacy mode Change-Id: Ica256bbdcba6d4616957ff38e63914dd15f645c6 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 881c7841c95dec392a66eef38a7112c1f385fdfa Original-Change-Id: I4c33f183ba4b301d68ae31c41fc6663f3be857b0 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241529 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9495 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Add function to apply PRR to a range of SPI flashDuncan Laurie
This function will use the next available/free protected range register to cover the specified region of flash and write protect it until the next reset. This will be used by the common MRC cache code to protect the RW_MRC_CACHE region after it is updated. In order to communicate to the common NVM code that this function is defined also enable CONFIG_MRC_SETTINGS_PROTECT variable. BUG=chrome-os-partner:28234 BRANCH=broadwell TEST=build and boot on samus Change-Id: I710c6a69f725479411ed978cc615e1bb78fb42b8 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 25365433be0f190e10a96d9946b8ea90c883b78a Original-Change-Id: I4a4cd27f9f4a94b9134dcba623f33b114299818f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241129 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9493 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Turn off panel backlight in S5 SMI handlerDuncan Laurie
In order for some panels to meet spec when the system is put into S5 by way of power button during firmware (i.e. not by the OS) then it needs to turn off the backlight and give it time to turn off before going into S5. If the OS properly sequences the panel down then the backlight enable bit will not be set in this step and nothing will happen. BUG=chrome-os-partner:33994 BRANCH=broadwell TEST=build and boot on samus Change-Id: Ic86f388218f889b1fe690cc1bfc5c3e233e95115 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: e3c9c131a87bae380e1fd3f96c9ad780441add56 Original-Change-Id: I43c5aee8e32768fc9e82790c9f7ceda0ed17ed13 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/240852 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9490 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Skip steps when disabling PCIe portDuncan Laurie
When disabling PCIe ports skip steps if no card is detected. This prevents the loop from timing out on each empty slot. BUG=chrome-os-partner:31424 BRANCH=broadwell TEST=build and boot on samus, check that this code is no longer timing out when disabling PCIe ports Change-Id: I84ee0e0e325784b3af06abe70420c07cf6e13ed2 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 4d759e2350dd00ceb7df196ac7008729dc1e4cef Original-Change-Id: Idd88f0f1191a5465a0d8dcca07b5c3a5c5ca8855 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/240851 Original-Reviewed-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9489 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Remove XHCI workarounds on WPTDuncan Laurie
The workarounds in ACPI methods for D0/D3 transition that are used on haswell/LPT do not all apply to broadwell/WPT. BUG=chrome-os-partner:28234 BRANCH=broadwell TEST=build and boot on samus, test USB functionality and wake and ensure the device still does into D3 state Change-Id: Ic3a75f5bf50e826ade7d942b48cfebb75cf976e6 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 1b54d105957ee80ca34048c42fb8f241731281cf Original-Change-Id: I877afd51fc6c9b7906e923b893fc31bdf2cd1090 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/240850 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9488 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Only do pre-graphics delay when running option romDuncan Laurie
This changes the broadwell graphics init path to only do the delay before initializing graphics when running chromeos if we are also going to execute the option rom. BUG=chrome-os-partner:33671 BRANCH=samus TEST=build and boot on samus Change-Id: Idb7d39b22f7f6dc3be6dfbd2fa3cc2e33d78a397 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: f7ed93504a74760f16acb8fb3c6c57ac514b7260 Original-Change-Id: I350f85738efe3d17152de4f025adbfd52ae15b95 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228882 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9474 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Fix PCIe ports programming sequences to enable HSIOPCWenkai Du
HSIOPC/GPIO71 is used to control power to VCCHSIO, VCCUSB3PLL and VCCSATA3PLL in S0. PCH will drive HSIOPC low when all the high speed I/O controllers (xHCI, SATA, GbE and PCIe) are idle. This patch added a few additional PCIe programming steps as required in 535127 BIOS Writer Guide Rev 2.3.0 to enable this power saving mode. BUG=none BRANCH=none TEST=tested on Paine watching GPIO71 toggling as expected Change-Id: Ica6954c125ec3129e2659168f1f23dc861ce5708 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: e38f9ef57c480ca5ee420020eb80a1adb3c381d3 Original-Change-Id: I88ef125c681c8631e8b887f7ccf017b90b8c0f10 Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/238580 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9482 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Update SATA Gen3 TX adjustment registersDuncan Laurie
The registers that were used here are for CPT/PPT and not for HSW/BDW chips. Update this to update just the Gen3 TX Output Voltage Downscale Amplitude Adjustment field in the SATA ECR T88. BUG=chrome-os-partner:28234 BRANCH=samus,auron TEST=build and boot on samus Change-Id: I94b702dc4a3c98678ba048ff9cfa4a85cc5b1eed Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 4c5816cc647b84266751e8a591eb85d7735fee12 Original-Change-Id: I98ec9678938a6675828721d5b57683077f555d21 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/238800 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9484 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Add a few bits to finalize stepDuncan Laurie
Added a few bits to set in finalize step from scrubbing BWG and reference code. BUG=chrome-os-partner:28234 BRANCH=broadwell TEST=build and boot on samus Change-Id: I7b0c4dd3f14c06175c973561760ad1bdafd46fbb Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 3802aef908849fe6ea2bb0034d884064154ae9da Original-Change-Id: Ia62055b32be039eef84a0f60f0ba307eb5dce6a1 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/239958 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9485 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10Broadwell: Set boot_mode of pei_data before running reference codeKenji Chen
Some actions are needed and some are not on the way resume from S3. BRANCH=master BUG=chrome-os-partner:33025,chrome-os-partner:33796 TEST=Built the image and confimed the boot_mode is correctly configured. Signed-off-by: Kenji Chen <kenji.chen@intel.com> Change-Id: If400df94f970a55f3921a5a2df24038d28beb489 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 40e719618ec101235cdb1755933e719abd873239 Original-Change-Id: Ia042ea8c63c2306e9d6a80d8efa66c4fc0722d85 Original-Reviewed-on: https://chromium-review.googlesource.com/229615 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Kenji Chen <kenji.chen@intel.com> Original-Tested-by: Kenji Chen <kenji.chen@intel.com> Reviewed-on: http://review.coreboot.org/9475 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Increase I2C SDA hold timing to 300nsChiranjeevi Rapolu
I2C bus SDA hold time can be marginal with 60ns value, especially when there is level shifter on the bus. So program it to 300ns based on Fast-mode specification, which is between 0 to 900ns. Apply the same timing for Standard-mode as well. Refer to original bug on BayTrail chrome-os-partner:28092, this is to carry forward the fix to Broadwell. BRANCH=chromeos-2013.04 BUG=chrome-os-partner:33378 TEST=suspend resume test, watch for I2C errors Change-Id: I93200b141602163903f5c9f52b94013bcf3382a5 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 72b82a1d5d836594e7d0f95972cc0dc91ae7ff8c Original-Change-Id: I995d6868a44f2578a6d0b18dd5e8548f3c3cd494 Original-Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/226386 Original-Reviewed-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9467 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: add RCBA posting read after writingWenkai Du
MEI PCI device has internal logic to flush out the posted writes before returning completion for non-posted request. When doing a RCBA write to function disable and then using the PCI CFG RD cycle, need to do RCBA posting read after writing to it to make sure the write went through. As Aaron sugegsted, abstracted function disable path to a common function. BUG=chrome-os-partner:33048 TEST=run warm and cold reboot testing Change-Id: I40d374f1712a9137b3b1eac6bbf2d71078840406 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: f10b368e01aae1fc5dda63f7ac0641dd2636c949 Original-Change-Id: I87aa8ccd604446263fc3621c9a01839a5a75b644 Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/223715 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9462 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10Broadwell: Synchronization with FRC for Root Port Power ManagementKenji Chen
BUG=chrome-os-partner:31424 TEST=Build a image and run on Samus proto boards to confirm if the settings are applied correctly. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Change-Id: I9147da86ce26ce7ef1c7034bc3dde0b27b63befa Original-Commit-Id: 1717505a3fdf41c5972b1c929872577247f9e3b5 Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Change-Id: I8138507506771148420a585fd12897a3bfe91916 Original-Reviewed-on: https://chromium-review.googlesource.com/221387 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9463 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10broadwell: Skip DDI-A enable in S3 resumeDuncan Laurie
DDI-A should not need re-enabled in the resume path, just the resume path when we did not execute VBIOS. BUG=chrome-os-partner:28234 BRANCH=samus,auron TEST=build and boot on samus, test suspend+resume Change-Id: I29d67591ac903bc1d712a956462bcf4a764ef2eb Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: c3fbeac10f3834a6d848154aa3449672871b13df Original-Change-Id: Iaf7d083c5c92c42b7a117e2d2c9546ada6bf5f76 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221988 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9461 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-17 10:36:26 +0000