Age | Commit message (Collapse) | Author |
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Move more Kconfig declarations to drivers/intel/fsp2_0/ and document
them properly. This way, we don't have to repeat dependencies and have
the prompts in a common place. We can also easily hide the prompt for
the header path in case the FSP repository is used.
SP platforms were skipped as their Kconfig is too weird but they
shouldn't hold other platforms back.
Change-Id: Iba5af49bcd15427e9eb9b111e6c4cc9bcb7adcae
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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For quite a bit now we are extending the FSP_USE_REPO option to be
available for all Intel SoCs. This results in a list being not only
hard to maintain but also prone to errors.
To change that behaviour this commit introduces the
HAVE_INTEL_FSP_REPO config option for SoCs that are supported from within
3rdparty/fsp.
If a SoC selects HAVE_INTEL_FSP_REPO the config option FSP_USE_REPO is
selected by default, but can be still deselected by the user in menuconfig.
Change-Id: I68ae373ce591f06073064aa75aac32ceca8fa1cc
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37582
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Make use of the publicly-available FSP binaries and headers for Comet
Lake. Also, remove the Comet Lake header files from src/vendorcode,
since they are no longer necessary.
Change-Id: I392cc7ee3bf5aa21753efd6eab4abd643b65ff94
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39372
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The cache as ram code will use one form of a non-eviction mode.
Change-Id: I418eb48434aa3da3bf5ca65315bb8c9077523966
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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With CL:1940398, this option is no longer needed. Recovery
requests are not cleared until kernel verification stage is
reached. If the FSP triggers any reboots, recovery requests
will be preserved. In particular:
- Manual requests will be preserved via recovery switch state,
whose behaviour is modified in CB:38779.
- Other recovery requests will remain in nvdata across reboot.
These functions now only work after verstage has run:
int vboot_check_recovery_request(void)
int vboot_recovery_mode_enabled(void)
int vboot_developer_mode_enabled(void)
BUG=b:124141368, b:35576380
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I52d17a3c6730be5c04c3c0ae020368d11db6ca3c
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38780
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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specific Kconfig
This patch moves common pch code SOC_INTEL_COMMON_BLOCK_THERMAL Kconfig selection
into SoC specific Kconfig selection as PCH thermal device is not available
with latest PCH (i.e. TGP and JSP).
Also added TODO for TGL thermal configuration as applicable.
TEST=Able to build and boot TGL RVP with this CL
Change-Id: Ibce17cc9f38fb666011ccd8f97bee63033ff5302
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38444
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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FSP logo handling used FspsConfig.LogoPtr and FspsConfig.LogoSize which
are chipset specific.
Create soc_load_logo() which will pass the logo pointer and size.
This function will call fsp_load_logo which will load the logo.
BUG=NA
TEST= Build and verified logo is displayed on Facebook Monolith
Change-Id: I30c7bdc0532ff8823e06f4136f210b542385d5ce
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37792
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This impacts boards:
hatch (&variants) and drallion.
Some variants like Puff can have up to 12 cores. coreboot should take
the min() where MAX_CPU is the upper bound.
Further to that, boards themseleves shouldn't be setting the MAX_CPUS,
the chipset should be and so do that.
BRANCH=none
BUG=b:146255011
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I284d027886f662ebb8414ea92540916ed19bc797
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
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We had to role the `fsp` submodule back for a minute due to a regression
with the Coffee Lake binary. Intel silently mixed FSP 2.1 features into
the Coffee Lake FSP which is supposed to be FSP 2.0. With the stack and
heap usage partitioned for FSP using coreboot's stack (config FSP_USES_
CB_STACK), it works again.
To make this even messier: We already selected this Kconfig option for
Whiskey Lake, which is supposed to use the very same FSP binary. So with
either submodule pointer, something was always broken :-/
Change-Id: Id2aa17aaa2c843dcc7e0fb28779d1e5948da83c9
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Mimoja <coreboot@mimoja.de>
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The name for the CoffeeLake FSP.fd was changed to Fsp.fd.
Therefore the CoffeLake / WhiskeyLake default path was
changed.
Change-Id: I0f51e378fcaacb25392d8940a342fc968c730157
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37564
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The romcc bootblock will be deprecated soon and most platforms use
C_ENVIRONMENT_BOOTBLOCK already. This patch drops the
CONFIG_C_ENVIRONMENT_BOOTBLOCK symbol and adds CONFIG_ROMCC_BOOTBLOCK
where needed.
Change-Id: I773a76aade623303b7cd95ebe9b0411e5a7ecbaf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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The common cbmem_top_chipset implementation uses the FSP bootloader HOB,
thus move it to the fsp driver which is a more appropriate place.
Change-Id: I914df51a7414eb72416f816ff8375a13d5716925
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36620
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: David Guckian
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Saving cbmem_top across stages is not needed anymore so EBDA should
not be used. The guard to cbmem_top_chipset implementation was
inappropriate.
Change-Id: Ibbb3534b88de4f7b6fc39675a77461265605e56e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
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The x86 timers are a bit of a mess. Cases where different stages use
different counters and timestamps use different counters from udelays.
The original intention was to only flip TSC_CONSTANT_RATE Kconfig
to NOT_CONSTANT_TSC_RATE. The name would be incorrect though, those
counters do run with a constant rate but we just lack tsc_freq_mhz()
implementation for three platforms.
Note that for boards with UNKNOWN_TSC_RATE=y, each stage will have a
slow run of calibrate_tsc_with_pit(). This is easy enough to fix with
followup implementation of tsc_freq_mhz() for the platforms.
Implementations with LAPIC_MONOTONIC_TIMER typically will not have
tsc_freq_mhz() implemented and default to UNKNOWN_TSC_RATE. However,
as they don't use TSC for udelay() the slow calibrate_tsc_with_pit()
is avoided.
Because x86/tsc_delay.tsc was using two different guards and nb/via/vx900
claimed UDELAY_TSC, but pulled UDELAY_IO implementation, we also switch
that romstage to use UDELAY_TSC.
Change-Id: I1690cb80295d6b006b75ed69edea28899b674b68
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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EBDA is not PCH related, thus move the Kconfig to the appropriate socs.
Change-Id: I216871ad1a8dd5bc294062a4e9b54eb51f71b781
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The current DCACHE_BSP_STACK_SIZE is set to 128KiB for CML & ICL when
FSP uses the same stack provided by coreboot. This patch updates it to
129KiB since the default value of DCACHE_BSP_STACK_SIZE must be
the sum of FSP-M stack requirement (128KiB) and CB romstage
stack requirement (~1KiB).
BUG=b:140268415
TEST=Build and boot CML-Hatch.
Change-Id: Icedff8b42e86dc095fb68deb0b8f80b2667cfeda
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36032
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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FSP BIOS 212 / 07.00.6C.40 for CNL/WHL supports FSP to use coreboot stack.
This change selects common stack config, that enables coreboot to support
share stack with FSP.
TEST=Boot to OS on WHL platform
Change-Id: I0778ee21cb4f66b8ec884b77788c05a73c609be6
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
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For CML & ICL, FSP requires at least heap = 0x10000 and stack = 0x20000.
Refer to FSP integration guide to know the exact FSP requirement.
BUG=b:140268415
TEST=Build and boot CML-Hatch and ICL.
Change-Id: Ic1463181b4a9dca136d00cb2f7e3cce4f7e57bd6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35301
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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* Add Kconfig to enable TXT
* Add possibility to add BIOS and SINIT ACMs
* Set default BIOS ACM alignment
* Increase FIT space if TXT is enabled
The following commits depend on the basic Kconfig infrastructure.
Intel TXT isn't supported until all following commits are merged.
Change-Id: I5f0f956d2b7ba43d4e7e0062803c6d8ba569a052
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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It is easier to track CAR_GLOBAL_MIGRATION which is
the approach to be deprecated with the next release.
This change enforces new policy; POSTCAR_STAGE=y is
not allowed together with CAR_GLOBAL_MIGRATION=y.
Change-Id: I0dbad6a14e68bf566ac0f151dc8ea259e5ae2250
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Almost all platforms force it on. Make it enabled by
default but under user control to optionally disable it.
Change-Id: I6b0f19c8bfd6ffed93023d57a1d28ca6acc06835
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add explicit CBMEM_STAGE_CACHE option. Rename
CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM to TSEG_STAGE_CACHE.
Platforms with SMM_TSEG=y always need to implement
stage_cache_external_region(). It is allowed to return with a
region of size 0 to effectively disable the cache.
There are no provisions in Kconfig to degrade from
TSEG_STAGE_CACHE to CBMEM_STAGE_CACHE.
As a security measure CBMEM_STAGE_CACHE default is changed to
disabled. AGESA platforms without TSEG will experience slower
S3 resume speed unless they explicitly select the option.
Change-Id: Ibbdc701ea85b5a3208ca4e98c428b05b6d4e5340
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch moves SOC_INTEL_COMMON_BLOCK_THERMAL selection from respective
soc/intel/{skl/cnl/icl} to common/pch/Kconfig.
Change-Id: I7c9c8a87cfc5cb4c2fa8b215e56cc35c1f0cce28
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34650
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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FSP v1263 for CML supports FSP to use coreboot stack. This change
selects common stack config, that enables coreboot to support
share stack with FSP.
BUG=b:133398276
Change-Id: I4098a4374363ca6f3c86c396d097f9eabc9a28fe
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34130
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable PCH thermal sensor for dynamic thermal shutdown for S0ix state.
BUG=None
BRANCH=None
TEST=Verified Thermal Device (B0: D18: F0) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE.
Change-Id: I50796bcf9e0d5a65cd7ba63fedd932967c4c1ff9
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34522
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The FSP_CAR option has additional configuration options whose default
values result in boot failures. Since default values should always boot,
default to the open-source CAR NEM Enhanced implementation instead. This
also allows us to get rid of an unnecessary vendor-specific special case.
Change-Id: I30b1808f91701c07dce6f1de08c213150e8a675a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34287
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch moves USE_LEGACY_8254_TIMER Kconfig into common/block/timer
for better code sharing. Also ported CB:33512 for SPT and ICP PCH.
Change-Id: Ic767ff97aaa3eb7fa35ffa38fa416d006eaa6e78
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: Id56139a3d0840684b13179821a77bc8ae28e05ae
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This is only a qualifier between TSEG and ASEG.
Change-Id: I8051df92d9014e3574f6e7d5b6f1d6677fe77c82
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch increases PRERAM_CBMEM_CONSOLE_SIZE to fix
*** Pre-CBMEM romstage console overflowed, log truncated! ***
issue.
TEST=Verified on Hatch CML platform.
Change-Id: I2de4ca2f2001b304850c27df1b3c3b2c827fe25a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Spoorthi K
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Enhance elog wake source information with more details about which USB port
resulted in a wake from S3 or S0ix.
BUG=b:123429132
BRANCH=none
TEST=``FW_NAME=hatch emerge-hatch chromeos-ec depthcharge vboot_reference
libpayload coreboot-private-files intel-cmlfsp coreboot-private-files-hatch
coreboot chromeos-bootimage``
Ensure /build/hatch/firmware/image-hatch.serial.bin has been built.
Plug a keyboard into a USB port on the DUT.
Switch the DUT to the console (Ctrl-Alt-F2, or use the AP console via
servo).
On the console, run ``powerd_dbus_suspend``.
Wait for the DUT to enter low power mode.
Verify low power mode by issuing the ``powerinfo`` command on the EC
console (via servo). Expect to see ``power state 4 = S0ix``.
Press a key on the USB keyboard.
The DUT wakes up.
On the console, run ``mosys eventlog list`` and look for the wake source.
156 | 2019-06-26 09:46:07 | S0ix Enter
157 | 2019-06-26 12:14:05 | S0ix Exit
158 | 2019-06-26 12:14:05 | Wake Source | Internal PME | 0
159 | 2019-06-26 12:14:05 | Wake Source | GPE # | 109
Program image-hatch.serial.bin into the DUT using flashrom.
Repeat the ``powerd_dbus_suspend``, ``powerinfo``, ``mosys eventlog list``
sequence.
12 | 2019-06-26 14:52:23 | S0ix Enter
13 | 2019-06-26 14:53:07 | S0ix Exit
14 | 2019-06-26 14:53:07 | Wake Source | PME - XHCI (USB 2.0 port) | 3
15 | 2019-06-26 14:53:07 | Wake Source | GPE # | 109
Change-Id: Ie9ef870e219733dea9806c766f5351db25689b32
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Instead of maintaining this in 3rdparty/blobs use the
3rdparty/intel-microcode which is maintained by Intel.
This allows for some finegrained control where family+model span
multiple targets.
Microcode updates present in
3rdparty/blobs/soc/intel/{baytrail,broadwell} are left out since those
contain updates not present in the Intel repo. Those are presumably
early CPU samples that did not end up in products.
The following MCU are get a new revision:
old:
sig 0x000306c3, pf_mask 0x32, 2018-04-02, rev 0x0025, size 23552
sig 0x00040651, pf_mask 0x72, 2018-04-02, rev 0x0024, size 22528
sig 0x000206a7, pf_mask 0x12, 2018-04-10, rev 0x002e, size 12288
sig 0x000306a9, pf_mask 0x12, 2018-04-10, rev 0x0020, size 13312
sig 0x000706a1, pf_mask 0x01, 2018-05-22, rev 0x0028, size 73728
sig 0x000506c9, pf_mask 0x03, 2018-05-11, rev 0x0032, size 16384
sig 0x000506ca, pf_mask 0x03, 2018-05-11, rev 0x000c, size 14336
sig 0x000806e9, pf_mask 0xc0, 2018-03-24, rev 0x008e, size 98304
sig 0x000906e9, pf_mask 0x2a, 2018-03-24, rev 0x008e, size 98304
sig 0x000906ea, pf_mask 0x22, 2018-05-02, rev 0x0096, size 97280
sig 0x000906eb, pf_mask 0x02, 2018-03-24, rev 0x008e, size 98304
sig 0x00050665, pf_mask 0x10, 2018-04-20, rev 0xe00000a, size 18432
sig 0x000506e3, pf_mask 0x36, 2018-04-17, rev 0x00c6, size 99328
sig 0x000906e9, pf_mask 0x2a, 2018-03-24, rev 0x008e, size 98304
sig 0x000406e3, pf_mask 0xc0, 2018-04-17, rev 0x00c6, size 99328
new:
sig 0x000306c3, pf_mask 0x32, 2019-02-26, rev 0x0027, size 23552
sig 0x00040651, pf_mask 0x72, 2019-02-26, rev 0x0025, size 21504
sig 0x000206a7, pf_mask 0x12, 2019-02-17, rev 0x002f, size 12288
sig 0x000306a9, pf_mask 0x12, 2019-02-13, rev 0x0021, size 14336
sig 0x000706a1, pf_mask 0x01, 2019-01-02, rev 0x002e, size 73728
sig 0x000506c9, pf_mask 0x03, 2019-01-15, rev 0x0038, size 17408
sig 0x000506ca, pf_mask 0x03, 2019-03-01, rev 0x0016, size 15360
sig 0x000806e9, pf_mask 0xc0, 2019-04-01, rev 0x00b4, size 99328
sig 0x000906e9, pf_mask 0x2a, 2019-04-01, rev 0x00b4, size 99328
sig 0x000906ea, pf_mask 0x22, 2019-04-01, rev 0x00b4, size 98304
sig 0x000906eb, pf_mask 0x02, 2019-04-01, rev 0x00b4, size 99328
sig 0x00050665, pf_mask 0x10, 2019-03-23, rev 0xe00000d, size 19456
sig 0x000506e3, pf_mask 0x36, 2019-04-01, rev 0x00cc, size 100352
sig 0x000906e9, pf_mask 0x2a, 2019-04-01, rev 0x00b4, size 99328
sig 0x000406e3, pf_mask 0xc0, 2019-04-01, rev 0x00cc, size 100352
Change-Id: Idcfb3c3c774e0b47637e1b5308c28002aa044f1c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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FSP sets the use of the 8254 timer via the Enable8254ClockGating
UPD, which defaults to enabled, overriding what is set by coreboot.
Per the FSP integration guide, this UPD needs to be disabled when
a legacy OS is booted (ie, when SeaBIOS is used as the payload).
Add a Kconfig option to set the UPD properly based on payload
selection, and remove the existing coreboot code in lpc.c since
it is either ineffective or being overridden by FSP.
Test: build/boot out-of-tree WHL board with both SeaBIOS and
Tianocore, ensure 8254 timer usage set correctly for each.
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: I0e888bf754cb72093f14fc02f39bddcd6d288203
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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SOC_INTEL_CANNONLAKE
This allows to use Kconfig options to differentiate between SOC
variants.
Change-Id: Ica11c68377e3d0dc8a8f48198e01a74d7bebe642
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33559
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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What it really means to do is to use different FSP headers.
Change-Id: I3c75d4aac8525ab2639608fb9c1b3a9afef0e943
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This patch provides an additional option to skip HECI function
disabling using SMM mode for WHL and CML platform, where FSP has
dedicated UPD to make HECI function disable.
User to select HECI_DISABLE_USING_SMM if FSP doesn't provided dedicated
UPD.
Right now CNL and ICL platform will use HECI_DISABLE_USING_SMM kconfig
to make HECI disable and WHL/CML has to rely on FSP to make HECI
disable.
Change-Id: If3b064f3c32877235916f966a01beb525156d188
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Re-add the Kconfig CONSOLE_UART_BASE_ADDRESS. It was lost by accident
on APL at least. It is used outside of soc/intel/ scope, e.g. to con-
figure SeaBIOS.
As we only ever configure a single UART for the coreboot console, we
don't need different addresses for each possible UART. Which saves
us a lot of code.
Change-Id: I28e1d98aa37a6acb57b98b8882fc4fa131d5d309
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Cannonlake PCH LP have total 6 pcie clocks and Cannonlake PCH H have
total 16 pcie clocks. It is different with pcie root port numbers.
BUG=CID 1381814
TEST=Build and boot up fine on sarien platform.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I909b5b584c596e6fe878ffe24d9cabc53c4576ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: John Zhao <john.zhao@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT in Kconfig
BUG=none
BRANCH=none
TEST=compiles
Change-Id: If5f59ea50c13bd1f279637e281468e6d0312dbab
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32486
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The name OPROM is somewhat inaccurate, since other steps to bring
up display and graphics are needed depending on mainboard/SoC.
This patch cleans up OPROM code nomenclature, and works towards
the goal of deprecating vboot1:
* Rename CONFIG_VBOOT_OPROM_MATTERS to
CONFIG_VBOOT_MUST_REQUEST_DISPLAY and clarify Kconfig
description
* Remove function vboot_handoff_skip_display_init
* Remove use of the VbInit oflag VB_INIT_OUT_ENABLE_DISPLAY
* Add |flags| field to vboot_working_data struct
* Create VBOOT_FLAG_DISPLAY_REQUESTED and set in vboot_handoff
BUG=b:124141368, b:124192753, chromium:948529
TEST=make clean && make test-abuild
TEST=build and flash eve device; attempt loading dev/rec modes
BRANCH=none
Change-Id: Idf111a533c3953448b4b9084885a9a65a2432a8b
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Update submodule pointer to pull in newly-updated Braswell FSP.
Adjust FSP_FD_PATH for soc/cannonlake due to filename case change.
Change-Id: I02ee0d32fd4c04cd4971eff20fc5a7de3f9b07ec
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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This change is mainly to control PlatformDebugConsent FSP UPD.
PlatformDebugConsent is enabled if SOC_INTEL_CANNONLAKE_DEBUG_CONSENT != 0.
PlatformDebugConsent in FspmUpd.h has the details.
BUG=b:130203864
TEST=boot ok and PlatformDebugConsent can be controlled by Kconfig
Change-Id: Ib845b5e42bc78fb352a0c97c6301f2aeca522f29
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32297
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit 41dad286d846819242a84fc65faed2bbb35845ac. The change will make s0ix fail on Sarien/Arcada Platform.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I169bc6f41fba82fcf515267e8e1d08aa5ee2dce4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32391
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Implement required soc side API to enable VMX support using CPU_COMMON
BUG=b:124518711
TEST= read msr 0x3a and verify vmx is enabled (value should be 5).
Change-Id: I33dbffa6301afabd688080751ba3b85a43e00156
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This patch performs MP initialization by FSP using coreboot MP
PPI service.
BUG=b:74436746
TEST=Able to perform MP initialization on WHL and CML platform.
Change-Id: I530d50e5aacc3cb9b625df14a50d4c5923e3fb4d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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Cannon Lake and family require that FSP-M component should be
XIP. This change selects FSP_M_XIP so that the right arguments are
passed into cbfstool when adding this component.
BUG=b:130306520
TEST=Verified that hatch boots fine to OS.
Change-Id: Ifd8a829ebdc7681c81ece4540aa38cdcea7b6fac
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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XIP_ROM_SIZE Kconfig option isn't used on Cannon Lake and
family. Thus, this change selects NO_FIXED_XIP_ROM_SIZE to indicate to
build system so that romstage can be placed in less rigid manner.
BUG=b:129802811
Change-Id: I5f3786396246c89b1039ba1b6b332a32e6a0345d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This patch adds SOC_INTEL_COMETLAKE Kconfig option.
Change-Id: I2b0c269ade84d72cffaf59a0b53e0d6e3a84b835
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/31282
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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SD controller in CNL-PCH provides a ability to configure the behavior of
SD_VDD1_PWR_EN# as an active high or low signal. FSP provides an UPD
"SdCardPowerEnableActiveHigh" to control the same.
However, for platforms using SD_VDD1_PWR_EN# as active high, the SDXC
card connector is always powered and may impact system power. This is because
SD_VDD1_PWR_EN# does not de-assert during SDXC D3 or when SD card is not
inserted.
Workaround is to change the pad ownership of SD_VDD1_PWR_EN to GPIO and
force the TX buffer to low in _PS3. And restore the pad mode to native
function in _PS0.
Hence add a Kconfig option to update the UPD, which the board can select
based on how the SD_VDD1_PWR_EN is implemented on it. And, the workaround
gets applied based on this config.
BUG=b:123350329
Change-Id: Iee262d7ecdf8c31362aec3d95dd9b3e8359e0c25
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31445
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch performs below tasks
1. Create SOC_INTEL_COMMON_CANNONLAKE_BASE kconfig.
2. Allow required SoC to select this kconfig to extend CANNONLAKE
SoC support and add incremental changes.
3. Select correct SoC support for hatch, sarien, cflrvps
and whlrvp.
* Hatch is WHL SoC based board
* Sarien is WHL SoC based board
* CFLRVP U/8/11 are CFL SoC based board
* WHLRVP is based on WHL SoC
4. Add correct FSP blobs path for WHL SoC based designs.
Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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