coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-09-09	soc/intel/cannonlake: Add PCIe ports on PCH-H	Patrick Rudolph
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-06	treewide: replace GPLv2 long form headers with SPDX header	Patrick Georgi
2020-05-06	treewide: Move "is part of the coreboot project" line in its own comment	Patrick Georgi
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2018-11-15	soc/intel/cannonlake: Make static IRQ mapping for CNP PCH pci devices	Subrata Banik
2018-10-09	soc/intel/cannonlake: Make correct IRQ mapping for CNL SA and PCH PCI devices	Subrata Banik
2017-09-19	soc/intel/cannonlake: Add PCIE IRQs	Bora Guvendik